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參數(shù)資料
| 型號： | PC87782 |
| 文件頁數(shù)： | 4/17頁 |
| 文件大?。?/td> | 114K |
| 代理商： | PC87782 |
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CR16A CPU Core
The PC87782 uses a CR16A CPU core module. This is the
same core used in other CompactRISC family members. The
core's Reduced Instruction Set Computer (RISC) architec-
ture is similar to that used in high-performance workstations.
The PC87782 RISC processor takes advantage of this archi-
tecture while maintaining the on-chip features and low cost of
an embedded controller.
The high performance of the CPU core results from the im-
plementation of a pipelined architecture with a two-bytes-per-
cycle pipelined system bus. As a result, the CPU can support
a peak execution rate of one instruction per clock cycle.
Compared with conventional RISC processors, the PC87782
differs in the following ways:
I
The CPU core uses on-chip rather than external memory.
This eliminates the need for large and complex bus inter-
face units.
I
All opcodes are 16 bits, so all basic instructions are just
two bytes long. (Additional bytes are sometimes required
for immediate values, so instructions can be two, four, or
six bytes long.)
I
Non-aligned access of multiple bytes is allowed. Each in-
struction can operate on 8-bit, 16-bit, or 32-bit data.
I
The device is designed to operate with a clock rate in the
10 to 20 MHz range rather than 100 MHz or more. Most
embedded systems face EMI and noise constraints that
limit clock speed to these lower ranges. A lower clock
speed means a simpler, less costly silicon implementa-
tion.
I
The instruction pipeline uses three stages rather than the
usual five or more used in workstation processors. A
smaller pipeline eliminates the need for costly branch pre-
diction mechanisms and bypass registers, while maintain-
ing adequate performance for typical embedded
controller applications.
Memory
The CompactRISC architecture supports a uniform linear ad-
dress space of 256K bytes. The PC87782 implementation of
this architecture uses only the lowest 64K bytes of address
space. Three types of on-chip memory occupy specific inter-
vals within this address space: 32K bytes of ROM program
memory and 2,784 bytes of static RAM memory.
The 32K bytes of ROM program memory are used to store
the application program. For prototype work, the 160-pin de-
vice supports the use of external memory in place of the on-
chip ROM.
The 2,784 bytes of static RAM are used for temporary stor-
age of data and for the program and interrupt stacks. Read
and write operations can be byte-wide or word-wide, depend-
ing on the instruction executed by the CPU. Each memory
access requires one clock cycle; no wait cycles or hold cy-
cles are required.
Input/Output Ports
Each device has 40 software-configurable I/O pins, orga-
nized into six 8-pin ports called Port B, Port C, Port F, Port L,
and Port I. Each pin can be configured to operate as a gen-
eral-purpose input or general-purpose output. In addition,
many I/O pins can be configured to operate as a designated
input or output for an on-chip peripheral module.
The I/O pin characteristics are fully programmable. Each pin
can be configured to operate as a TRI-STATE output, push-
pull output, weak pull-up input, or high-impedance input. All
input pins are equipped with Schmitt triggers for noise resis-
tance.
Bus Interface Unit
The Bus Interface Unit (BIU) controls the interface between
the on-chip modules to the internal core bus (and to off-chip
memory or I/O, if used). It determines the configured param-
eters for bus access (such as the number of wait states for
memory access) and issues the appropriate bus signals for
each requested access.
The BIU uses a set of control registers to determine how
many wait states and hold states are to be used when ac-
cessing different types of memory. Upon start-up of the de-
vice, these registers must be programmed with appropriate
values so that the minimum allowable number states is used.
Interrupts
The Interrupt Control Unit (ICU) receives interrupt requests
from internal and external sources and generates interrupts
to the CPU. An interrupt is an event that temporarily stops the
normal flow of program execution and causes a separate in-
terrupt service routine to be executed. After the interrupt is
serviced, CPU execution continues with the next instruction
in the program following the point of interruption.
Interrupts from the on-chip peripherals and interface mod-
ules are all maskable interrupts; they can be enabled or dis-
abled by the software. There are 16 of these interrupts,
organized into 16 predetermined levels of priority.
The highest-priority interrupt is the Non-Maskable Interrupt
(NMI), which is generated by a signal received on the PFAIL
input pin.
Multi-Input Wake-Up
The Multi-Input Wake-up (MIWU) modules can be used for
either of two purposes: to wake up (exit from) from the Idle
mode upon the occurrence of specified events; or to provide
general-purpose edge-triggered maskable interrupts from
external sources. One eight-channel MIWU module gener-
ates a combined interrupt to the CPU based on the signals
received on its eight input channels, which are alternate func-
tions of Port L. Channels can be individually enabled or dis-
abled, and programmed to respond to positive or negative
edges. Another MIWU module generates a combined inter-
rupt to the CPU based on internal events: a Timer T0 event,
a Host Bus read or write, or an SMB wake-up event.
Clock Generator
The Clock Generator module generates a high-speed main
system clock (4 to 20 MHz) based on a slow (32.768 kHz)
clock signal or crystal network. An on-chip oscillator gener-
ates the high-speed clock and locks on to the programmed
rate, using the low-speed clock as a reference.
The slow clock is also used for operating the device in Idle
mode. During Idle mode, the fast clock oscillator continues to
operate but is disconnected from the rest of the device to re-
duce power consumption.
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相關(guān)代理商/技術(shù)參數(shù) |
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