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參數(shù)資料
| 型號： | PC87782 |
| 文件頁數(shù)： | 10/17頁 |
| 文件大小： | 114K |
| 代理商： | PC87782 |
10
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OSCOUT
Analog in
Analog out
Analog I/O
Analog FB
MII In
Oscillator Output [not characterized]
A/D Analog Input signal
D/A Analog output signal
A/D Analog input/output signal
A/D Op-Amp Feedback
Ethernet IEEE 802.3u compliant input
V
IH
V
IL
(TTL)
V
TRH
V
TRL
MII Out
V
OHm
V
OLm
Ethernet IEEE 802.3u compliant output
Table 3 Input Pins
Signal
Type
Pin Number
No. of
Sig Pins
Function
100-pin
160-pin
32KCLKIN
AMP(1,0)
ENV(1,0)
ENV2
TTL
Analog In
STRAP
STRAP
1
2
2
32.768 KHz Oscillator Clock Input.
Analog Inputs to Op-Amps
Environment select strap pins. These pins define the
device environment. They are sampled on all resets
except HMR. ENV2 is permanently high in the 100-pin
package.
Host Address line used in conjunction with the chip-
select inputs to address registers on the Host Interface.
Host I/O Read. Active-low input that signals an I/O data
read by the host processor.
Host I/O Write. Active-low input that signals an I/O data
write by the host processor.
Host Chip Select A. Active-low input that indicates an
access to Channel A by the host processor.
Host Chip Select B. Active-low input that indicates an
access to Channel B by the host processor.
Host Master Reset
Host Power On. Indicates that the host power supply is
on, and the host bus interface signals are valid. While
HPWRON is low, the host inputs are ignored, and all
outputs float.
NAND Test Mode / ISE TRI-STATE Mode
Power Fail Detected Input
Master Reset. A low level resets the controller and
inhibits HFCG frequency locking.
MII Input data.
MII Receive Clock
MII Receive Data Valid
MII Receive Error
MII Collision Detect
MII Carrier Sense
Transmit Clock Input
ISE Interrupt. reserved for use by the development
system.
N/A
1
HA
TTL
1
HIOR
TTL
1
HIOW
TTL
1
HCSA
TTL
1
HCSB
TTL
1
HMR
HPWRON
Schmitt
Schmitt
1
1
NANDEN
PFAIL
RESET
Schmitt
Schmitt
Schmitt
1
1
1
RXD0-3
RX_CLK
RX_DV
RX_ER
COL
CRS
TX_CLK
ISE
MII In
MII In
MII In
MII In
MII In
MII In
MII In
Schmitt
4
1
1
1
1
1
1
N/A
1
Table 2 Pin Descriptions
Signal Type
Input
Parameters
Output
Parameters
Buffer Description
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