參數(shù)資料
型號(hào): P89CV51RD2FA,512
廠商: NXP Semiconductors
文件頁(yè)數(shù): 67/76頁(yè)
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 64K 44-PLCC
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 26
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: EBI/EMI,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 64KB(64K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 706 (CN2011-ZH PDF)
其它名稱: 568-4256-5
935283268512
P89CV51RD2FA
P89CV51RB2_RC2_RD2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 25 August 2009
7 of 76
NXP Semiconductors
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
P2[1]/A9
25
19
I/O
P2[1] — Port 2 bit 1.
O
A9 — Address bit 9.
P2[2]/A10
26
20
I/O
P2[2] — Port 2 bit 2.
O
A10 — Address bit 10.
P2[3]/A11
27
21
I/O
P2[3] — Port 2 bit 3.
O
A11 — Address bit 11.
P2[4]/A12
28
22
I/O
P2[4] — Port 2 bit 4.
O
A12 — Address bit 12.
P2[5]/A13
29
23
I/O
P2[5] — Port 2 bit 5.
O
A13 — Address bit 13.
P2[6]/A14
30
24
I/O
P2[6] — Port 2 bit 6.
O
A14 — Address bit 14.
P2[7]/A15
31
25
I/O
P2[7] — Port 2 bit 7.
O
A15 — Address bit 15.
P3[0] to P3[7]
I/O with
internal
pull-up
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
pins are pulled HIGH by the internal pull-ups when 1s are written to them
and can be used as inputs in this state. As inputs, Port 3 pins that are
externally pulled LOW will source current (IIL) because of the internal
pull-ups.
P3[0]/RXD
11
5
I/O
P3[0] — Port 3 bit 0.
I
RXD — Serial input port.
P3[1]/TXD
13
7
I/O
P3[1] — Port 3 bit 1.
O
TXD — Serial output port.
P3[2]/INT0
14
8
I/O
P3[2] — Port 3 bit 2.
I
INT0 — External interrupt 0 input.
P3[3]/INT1
15
9
I/O
P3[3] — Port 3 bit 3.
I
INT1 — External interrupt 1 input.
P3[4]/T0
16
10
I/O
P3[4] — Port 3 bit 4.
I
T0 — External count input to timer/counter 0.
P3[5]/T1
17
11
I/O
P3[5] — Port 3 bit 5.
I
T1 — External count input to timer/counter 1.
P3[6]/WR
18
12
I/O
P3[6] — Port 3 bit 6.
O
WR — External data memory write strobe.
P3[7]/RD
19
13
I/O
P3[7] — Port 3 bit 7.
O
RD — External data memory read strobe.
PSEN
32
26
O
Program Store Enable: PSEN is the read strobe for external program
memory. When the device is executing from internal program memory,
PSEN is inactive (HIGH). When the device is executing code from external
program memory, PSEN is activated twice each machine cycle, except that
two PSEN activations are skipped during each access to external data
memory.
Table 3.
P89CV51RB2/RC2/RD2 Pin description …continued
Symbol
Pin
Type
Description
PLCC44
TQFP44
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