參數(shù)資料
型號: P89CV51RD2FA,512
廠商: NXP Semiconductors
文件頁數(shù): 31/76頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 64K 44-PLCC
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 26
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: EBI/EMI,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
產(chǎn)品目錄頁面: 706 (CN2011-ZH PDF)
其它名稱: 568-4256-5
935283268512
P89CV51RD2FA
P89CV51RB2_RC2_RD2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 25 August 2009
37 of 76
NXP Semiconductors
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
6.6.5 Framing error
Framing Error (FE) is reported in the SCON.7 bit if SMOD0 (PCON.6) = 1. If SMOD0 = 0,
SCON.7 is the SM0 bit for the UART, it is recommended that SM0 is set up before SMOD0
is set to 1.
Table 24.
SCON - Serial port control register (address 98H) bit allocation
Bit addressable; reset value: 00H.
Bit
7
6
5
4
3
2
1
0
Symbol
SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
Table 25.
SCON - Serial port control register (address 98H) bit description
Bit
Symbol
Description
7
SM0/FE
The usage of this bit is determined by SMOD0 in the PCON register. If
SMOD0 = 0, this bit is SM0, which with SM1, denes the serial port
mode. If SMOD0 = 1, this bit is FE (Framing Error). FE is set by the
receiver when an invalid stop bit is detected. Once set, this bit cannot
be cleared by valid frames but can only be cleared by software. (Note:
It is recommended to set up UART mode bits SM0 and SM1 before
setting SMOD0 to 1.)
6
SM1
With SM0, denes the serial port mode; see Table 26.
5
SM2
Enables the multiprocessor communication feature in modes 2 and 3.
In Mode 2 or 3, if SM2 is set to 1, then RI will not be activated if the
received 9th data bit (RB8) is 0. In Mode 1, if SM2 = 1 then RI will not
be activated if a valid stop bit was not received. In Mode 0, SM2
should be 0.
4
REN
Enables serial Reception. Set by software to enable reception. Clear
by software to disable reception.
3
TB8
The 9th data bit that will be transmitted in modes 2 and 3. Set or clear
by software as desired.
2
RB8
In modes 2 and 3, is the 9th data bit that was received. In mode 1, if
SM2 = 0, RB8 is the stop bit that was received. In Mode 0, RB8 is
undened.
1
TI
Transmit Interrupt ag. Set by hardware at the end of the 8th bit time in
Mode 0, or at the stop bit in the other modes, in any serial
transmission. Must be cleared by software.
0
RI
Receive Interrupt ag. Set by hardware at the end of the 8th bit time in
Mode 0, or approximately halfway through the stop bit time in all other
modes. (See SM2 for exceptions). Must be cleared by software.
Table 26.
SCON - Serial port control register (address 98H) SM0/SM1 mode denition
SM0, SM1
UART mode
Baud rate
0 0
0: shift register
CPU clock / 6
0 1
1: 8-bit UART
variable
1 0
2: 9-bit UART
CPU clock / 32 or CPU clock / 16
1 1
3: 9-bit UART
variable
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