參數(shù)資料
型號(hào): P89CV51RB2FBC,557
廠(chǎng)商: NXP Semiconductors
文件頁(yè)數(shù): 59/76頁(yè)
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 16K 44-TQFP
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 800
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: EBI/EMI,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 16KB(16K x 8)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤(pán)
其它名稱(chēng): 568-4253
935284179557
P89CV51RB2FBC
P89CV51RB2_RC2_RD2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 25 August 2009
62 of 76
NXP Semiconductors
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
9.
Dynamic characteristics
[1]
Tcy(clk) = 1 / fosc.
[2]
Calculated values are for 6-clock mode only.
Table 55.
Dynamic characteristics
Over operating conditions: load capacitance for port 0, ALE, and PSEN = 100 pF; load capacitance for all other
outputs = 80 pF.
Tamb = 40 °C to +85 °C; VDD = 4.5 V to 5.5 V; VSS =0V.[1][2]
Symbol Parameter
Conditions
Min
Typ
Max
Unit
fosc
oscillator frequency
12-clock mode
0
-
40
MHz
6-clock mode
0
-
20
MHz
IAP
0.25
-
40
MHz
tLHLL
ALE pulse width
2Tcy(clk) 15
-
ns
tAVLL
address valid to ALE LOW time
Tcy(clk) 15
-
ns
tLLAX
address hold after ALE LOW time
Tcy(clk) 15
-
ns
tLLIV
ALE LOW to valid instruction in time
-
4Tcy(clk) 45
ns
tLLPL
ALE LOW to PSEN LOW time
Tcy(clk) 15
-
ns
tPLPH
PSEN pulse width
3Tcy(clk) 15
-
ns
tPLIV
PSEN LOW to valid instruction in
time
--
3Tcy(clk) 50
ns
tPXIX
input instruction hold after PSEN time
0
-
ns
tPXIZ
input instruction oat after PSEN time
-
Tcy(clk) 15
ns
tPXAV
PSEN to address valid time
Tcy(clk) 8-
-
ns
tAVIV
address to valid instruction in time
-
5Tcy(clk) 60
ns
tPLAZ
PSEN LOW to address oat time
-
10
ns
tRLRH
RD LOW pulse width
6Tcy(clk) 30
-
ns
tWLWH
WR LOW pulse width
6Tcy(clk) 30
-
ns
tRLDV
RD LOW to valid data in time
-
5Tcy(clk) 50
ns
tRHDX
data hold after RD time
0
-
ns
tRHDZ
data oat after RD time
-
2Tcy(clk) 12
ns
tLLDV
ALE LOW to valid data in time
-
8Tcy(clk) 50
ns
tAVDV
address to valid data in time
-
9Tcy(clk) 75
ns
tLLWL
ALE LOW to RD or WR LOW time
3Tcy(clk) 15
-
3Tcy(clk) + 15
ns
tAVWL
address to RD or WR LOW time
4Tcy(clk) 30
-
ns
tWHQX
data hold after WR time
Tcy(clk) 20
-
ns
tQVWH
data output valid to WR HIGH time
7Tcy(clk) 50
-
ns
tRLAZ
RD LOW to address oat time
-
0
ns
tWHLH
RD or WR HIGH to ALE HIGH time
Tcy(clk) 15
-
Tcy(clk) + 15
ns
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