參數(shù)資料
型號: P89CV51RB2FBC,557
廠商: NXP Semiconductors
文件頁數(shù): 56/76頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 16K 44-TQFP
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 800
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: EBI/EMI,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
其它名稱: 568-4253
935284179557
P89CV51RB2FBC
P89CV51RB2_RC2_RD2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 25 August 2009
6 of 76
NXP Semiconductors
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
P0[6]/AD6
37
31
I/O
P0[6] — Port 0 bit 6.
I/O
AD6 — Address/data bit 6.
P0[7]/AD7
36
30
I/O
P0[7] — Port 0 bit 7.
I/O
AD7 — Address/data bit 7.
P1[0] to P1[7]
I/O with
internal
pull-up
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The
Port 1 pins are pulled HIGH by the internal pull-ups when 1s are written to
them and can be used as inputs in this state. As inputs, Port 1 pins that are
externally pulled LOW will source current (IIL) because of the internal
pull-ups. P1[5], P1[6], P1[7] have high current drive of 16 mA.
P1[0]/T2
2
40
I/O
P1[0] — Port 1 bit 0.
I/O
T2 — External count input to timer/counter 2 or clock-out from timer/counter
2.
P1[1]/T2EX
3
41
I/O
P1[1] — Port 1 bit 1.
I
T2EX: Timer/counter 2 capture/reload trigger and direction control.
P1[2]/ECI
4
42
I/O
P1[2] — Port 1 bit 2.
I
ECI — External clock input. This signal is the external clock input for the
PCA.
P1[3]/CEX0
5
43
I/O
P1[3] — Port 1 bit 3.
I/O
CEX0 — Capture/compare external I/O for PCA Module 0. Each
capture/compare module connects to a Port 1 pin for external I/O. When not
used by the PCA, this pin can handle standard I/O.
P1[4]/CEX1/
SS
6
44
I/O
P1[4] — Port 1 bit 4.
I/O
CEX1 — Capture/compare external I/O for PCA Module 1.
I
SS — Slave Select input for SPI.
P1[5]/CEX2/
MOSI
7
1
I/O
P1[5] — Port 1 bit 5.
I/O
CEX2 — Capture/compare external I/O for PCA Module 2.
I/O
MOSI — Master output/slave input for SPI.
P1[6]/CEX3/
MISO
8
2
I/O
P1[6] — Port 1 bit 6.
I/O
CEX3 — Capture/compare external I/O for PCA Module 3.
I/O
MISO — Master input/slave output for SPI.
P1[7]/CEX4/
SPICLK
9
3
I/O
P1[7] — Port 1 bit 7.
I/O
CEX4 — Capture/compare external I/O for PCA Module 4.
I/O
SPICLK — Serial clock input/output for SPI.
P2[0] to P2[7]
I/O with
internal
pull-up
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2
pins are pulled HIGH by the internal pull-ups when 1s are written to them
and can be used as inputs in this state. As inputs, Port 2 pins that are
externally pulled LOW will source current (IIL) because of the internal
pull-ups. Port 2 sends the high-order address byte during fetches from
external program memory and during accesses to external data memory
that use 16-bit address (MOVX @DPTR). In this application, it uses strong
internal pull-ups when transitioning to 1s.
P2[0]/A8
24
18
I/O
P2[0] — Port 2 bit 0.
O
A8 — Address bit 8.
Table 3.
P89CV51RB2/RC2/RD2 Pin description …continued
Symbol
Pin
Type
Description
PLCC44
TQFP44
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