參數(shù)資料
型號(hào): P89CV51RB2FBC,557
廠商: NXP Semiconductors
文件頁(yè)數(shù): 45/76頁(yè)
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 16K 44-TQFP
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 800
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: EBI/EMI,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 16KB(16K x 8)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤(pán)
其它名稱(chēng): 568-4253
935284179557
P89CV51RB2FBC
P89CV51RB2_RC2_RD2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 25 August 2009
5 of 76
NXP Semiconductors
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
5.2 Pin description
Fig 3.
TQFP44 pin conguration
P89CV51RB2/RC2/RD2
P1[5]/CEX2/MOSI
P0[4]/AD4
P1[6]/CEX3/MISO
P0[5]/AD5
P1[7]/CEX4/SPICLK
P0[6]/AD6
RST
P0[7]/AD7
P3[0]/RXD
n.c.
P3[1]/TXD
P2[7]/A15
P3[4]/T0
P2[6]/A14
P3[5]/T1
P2[5]/A13
P1[4]/CEX1/SS
P1[3]/CEX0
XTAL2
P1[2]/ECI
XTAL1
P1[1]/T2EX
V
SS
P1[0]/T2
n.c.
P2[0]/A8
V
DD
P2[1]/A9
P0[0]/AD0
P2[2]/A10
P0[1]/AD1
P2[3]/A11
P0[2]/AD2
P2[4]/A12
P0[3]/AD3
002aac961
EA
ALE
PSEN
P3[6]/WR
P3[7]/RD
P3[3]/INT1
P3[2]/INT0
n.c.
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
Table 3.
P89CV51RB2/RC2/RD2 Pin description
Symbol
Pin
Type
Description
PLCC44
TQFP44
P0[0] to P0[7]
I/O
Port 0: Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that
have 1s written to them oat, and in this state can be used as
high-impedance inputs. Port 0 is also the multiplexed low-order address
and data bus during accesses to external code and data memory. In this
application, it uses strong internal pull-ups when transitioning to 1s.
External pull-ups are required when used as a general purpose I/O port.
P0[0]/AD0
43
37
I/O
P0[0] — Port 0 bit 0.
I/O
AD0 — Address/data bit 0.
P0[1]/AD1
42
36
I/O
P0[1] — Port 0 bit 1.
I/O
AD1 — Address/data bit 1.
P0[2]/AD2
41
35
I/O
P0[2] — Port 0 bit 2.
I/O
AD2 — Address/data bit 2.
P0[3]/AD3
40
34
I/O
P0[3] — Port 0 bit 3.
I/O
AD3 — Address/data bit 3.
P0[4]/AD4
39
33
I/O
P0[4] — Port 0 bit 4.
I/O
AD4 — Address/data bit 4.
P0[5]/AD5
38
32
I/O
P0[5] — Port 0 bit 5.
I/O
AD5 — Address/data bit 5.
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