參數(shù)資料
型號: P89CV51RB2FBC,557
廠商: NXP Semiconductors
文件頁數(shù): 49/76頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 16K 44-TQFP
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 800
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: EBI/EMI,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
其它名稱: 568-4253
935284179557
P89CV51RB2FBC
P89CV51RB2_RC2_RD2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 25 August 2009
53 of 76
NXP Semiconductors
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
6.10 Security bits
The security bits protect against software piracy and prevent the contents of the ash from
being read by unauthorized parties in Parallel programmer mode and ISP mode. Since the
end application might need to erase pages and read from the code memory, the security
bits have no effect in IAP mode. However, the security bits’ programmed/erased state may
be read using IAP function calls allowing the end-user code to limit access, if desired. The
security bits and their effects are shown in Table 40.
Note: On this device, MOVC instructions executed from external code memory are
prevented from fetching code bytes from internal code memory.
6.11 Interrupt priority and polling sequence
The device supports eight interrupt sources under a four-level priority scheme. Table 41
summarizes the polling sequence of the supported interrupts. Note that the SPI serial
interface and the UART share the same interrupt vector; see Figure 25.
Table 40.
Security bit functions
Security bit
Description
1
Write protect. When programmed, prohibits further erasing or
programming, except to program other security bits or a chip erase.
2
Read protect. When programmed, inhibits reading of user code memory.
3
External execution inhibit. When programmed, prevents any execution of
instructions from external code memory.
Table 41.
Interrupt polling sequence
Description
Interrupt ag
Vector address Interrupt
enable
Interrupt
priority
Service
priority
Wake-up
Power-down
External
Interrupt 0
IE0
0003H
EX0
PX0/PX0H
1 (highest)
yes
T0
TF0
000BH
ET0
PT0/PT0H
2
no
External
Interrupt 1
IE1
0013H
EX1
PX1/PX1H
3
yes
T1
TF1
001BH
ET1
PT1/PT1H
4
no
UART
TI/RI
0023H
ES
PS/PSH
5
no
SPI
SPIF
0023H
ES
PS/PSH
5
no
PCA
CF/CCFn
0033H
EC
PPC/PPCH
7
no
T2
TF2, EXF2
003BH
ET2
PT2/PT2H
6
no
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