參數(shù)資料
型號(hào)： P87LPC769HD512
廠商： NXP Semiconductors N.V.
元件分類： 8位微控制器
英文描述： IC-SM-8-BIT MCU
中文描述： 集成電路釤8位微控制器
文件頁數(shù)： 36/61頁
文件大小： 306K
代理商： P87LPC769HD512
Philips Semiconductors
Preliminary specification
87LPC769
Low power, low price, low pin count (20 pin)
microcontroller with 4 kB OTP 8-bit A/D, and DAC
2001 Jan 11
33
Timer/Counters
The 87LPC769 has two general purpose counter/timers which are
upward compatible with the standard 80C51 Timer 0 and Timer 1.
Both can be configured to operate either as timers or event counters
(see Figure 25). An option to automatically toggle the T0 and/or T1
pins upon timer overflow has been added.
In the “Timer” function, the register is incremented every machine
cycle. Thus, one can think of it as counting machine cycles. Since a
machine cycle consists of 6 CPU clock periods, the count rate is 1/6
of the CPU clock frequency. Refer to the section Enhanced CPU for
a description of the CPU clock.
In the “Counter” function, the register is incremented in response to
a 1-to-0 transition at its corresponding external input pin, T0 or T1.
In this function, the external input is sampled once during every
machine cycle. When the samples of the pin state show a high in
one cycle and a low in the next cycle, the count is incremented. The
new count value appears in the register during the cycle following
the one in which the transition was detected. Since it takes 2
machine cycles (12 CPU clocks) to recognize a 1-to-0 transition, the
maximum count rate is 1/6 of the CPU clock frequency. There are no
restrictions on the duty cycle of the external input signal, but to
ensure that a given level is sampled at least once before it changes,
it should be held for at least one full machine cycle.
The “Timer” or “Counter” function is selected by control bits C/T in
the Special Function Register TMOD. In addition to the “Timer” or
“Counter” selection, Timer 0 and Timer 1 have four operating
modes, which are selected by bit-pairs (M1, M0) in TMOD. Modes 0,
1, and 2 are the same for both Timers/Counters. Mode 3 is different.
The four operating modes are described in the following text.
BIT
TMOD.7
SYMBOL
GATE
FUNCTION
Gating control for Timer 1. When set, Timer/Counter is enabled only while the INT1 pin is high and
the TR1 control pin is set. When cleared, Timer 1 is enabled when the TR1 control bit is set.
Timer or Counter Selector for Timer 1. Cleared for Timer operation (input from internal system clock.)
Set for Counter operation (input from T1 input pin).
Mode Select for Timer 1 (see table below).
Gating control for Timer 0. When set, Timer/Counter is enabled only while the INT0 pin is high and
the TR0 control pin is set. When cleared, Timer 0 is enabled when the TR0 control bit is set.
Timer or Counter Selector for Timer 0. Cleared for Timer operation (input from internal system clock.)
Set for Counter operation (input from T0 input pin).
Mode Select for Timer 0 (see table below).
Timer Mode
8048 Timer “TLn” serves as 5-bit prescaler.
16-bit Timer/Counter “THn” and “TLn” are cascaded; there is no prescaler.
8-bit auto-reload Timer/Counter. THn holds a value which is loaded into TLn when it overflows.
Timer 0 is a dual 8-bit Timer/Counter in this mode. TL0 is an 8-bit Timer/Counter controlled by the
standard Timer 0 control bits. TH0 is an 8-bit timer only, controlled by the Timer 1 control bits (see
text). Timer 1 in this mode is stopped.
TMOD.6
C/T
TMOD.5, 4
TMOD.3
M1, M0
GATE
TMOD.2
C/T
TMOD.1, 0
M1, M0
M1, M0
0 0
0 1
1 0
1 1
M0
SU01171
M1
C/T
GATE
M0
M1
C/T
GATE
0
1
2
3
4
5
6
7
TMOD
Reset Value: 00h
Not Bit Addressable
Address: 89h
Figure 25. Timer/Counter Mode Control Register (TMOD)
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