參數(shù)資料
型號(hào)： P87LPC769HD512
廠商： NXP Semiconductors N.V.
元件分類： 8位微控制器
英文描述： IC-SM-8-BIT MCU
中文描述： 集成電路釤8位微控制器
文件頁(yè)數(shù)： 17/61頁(yè)
文件大小： 306K
代理商： P87LPC769HD512
Philips Semiconductors
Preliminary specification
87LPC769
Low power, low price, low pin count (20 pin)
microcontroller with 4 kB OTP 8-bit A/D, and DAC
2001 Jan 11
14
Analog Comparators
Two analog comparators are provided on the 87LPC769. Input and
output options allow use of the comparators in a number of different
configurations. Comparator operation is such that the output is a
logical one (which may be read in a register and/or routed to a pin)
when the positive input (one of two selectable pins) is greater than
the negative input (selectable from a pin or an internal reference
voltage). Otherwise the output is a zero. Each comparator may be
configured to cause an interrupt when the output value changes.
Comparator Configuration
Each comparator has a control register, CMP1 for comparator 1 and
CMP2 for comparator 2. The control registers are identical and are
shown in Figure 5.
The overall connections to both comparators are shown in Figure 6.
There are eight possible configurations for each comparator, as
determined by the control bits in the corresponding CMPn register:
CPn, CNn, and OEn. These configurations are shown in Figure 7.
When each comparator is first enabled, the comparator output and
interrupt flag are not guaranteed to be stable for 10 microseconds.
The corresponding comparator interrupt should not be enabled
during that time, and the comparator interrupt flag must be cleared
before the interrupt is enabled in order to prevent an immediate
interrupt service.
BIT
CMPn.7, 6
CMPn.5
SYMBOL
—
CEn
FUNCTION
Reserved for future use. Should not be set to 1 by user programs.
Comparator enable. When set by software, the corresponding comparator function is enabled.
Comparator output is stable 10 microseconds after CEn is first set.
Comparator positive input select. When 0, CINnA is selected as the positive comparator input. When
1, CINnB is selected as the positive comparator input.
Comparator negative input select. When 0, the comparator reference pin CMPREF is selected as
the negative comparator input. When 1, the internal comparator reference V
ref
is selected as the
negative comparator input.
Output enable. When 1, the comparator output is connected to the CMPn pin if the comparator is
enabled (CEn = 1). This output is asynchronous to the CPU clock.
Comparator output, synchronized to the CPU clock to allow reading by software. Cleared when the
comparator is disabled (CEn = 0).
Comparator interrupt flag. This bit is set by hardware whenever the comparator output COn changes
state. This bit will cause a hardware interrupt if enabled and of sufficient priority. Cleared by
software and when the comparator is disabled (CEn = 0).
CMPn.4
CPn
CMPn.3
CNn
CMPn.2
OEn
CMPn.1
COn
CMPn.0
CMFn
CMFn
SU01152
COn
OEn
CNn
CPn
CEn
—
—
0
1
2
3
4
5
6
7
CMPn
Reset Value: 00h
Not Bit Addressable
Address: ACh for CMP1, ADh for CMP2
Figure 5. Comparator Control Registers (CMP1 and CMP2)
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