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| 型號： | P87LPC769HD512 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 8位微控制器 |
| 英文描述： | IC-SM-8-BIT MCU |
| 中文描述： | 集成電路釤8位微控制器 |
| 文件頁數(shù)： | 33/61頁 |
| 文件大小： | 306K |
| 代理商： | P87LPC769HD512 |
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Philips Semiconductors
Preliminary specification
87LPC769
Low power, low price, low pin count (20 pin)
microcontroller with 4 kB OTP 8-bit A/D, and DAC
2001 Jan 11
30
For correct activation of Brownout Detect, the V
DD
fall time must be
no faster than 50 mV/
μ
s. When V
DD
is restored, is should not rise
faster than 2 mV/
μ
s in order to insure a proper reset.
The brownout voltage (BOV) bit in the EPROM configuration register
UCFG1 must be programmed to a zero.
If the Brownout Detect function is not required in an application, it
may be disabled, thus saving power. Brownout Detect is disabled by
setting the control bit BOD in the AUXR1 register (AUXR1.6).
Power On Detection
The Power On Detect has a function similar to the Brownout Detect,
but is designed to work as power comes up initially, before the
power supply voltage reaches a level where Brownout Detect can
work. When this feature is activated, the POF flag in the PCON
register is set to indicate an initial power up condition. The POF flag
will remain set until cleared by software.
Power Reduction Modes
The 87LPC769 supports Idle and Power Down modes of power
reduction.
Idle Mode
The Idle mode leaves peripherals running in order to allow them to
activate the processor when an interrupt is generated. Any enabled
interrupt source or Reset may terminate Idle mode. Idle mode is
entered by setting the IDL bit in the PCON register (see Figure 22).
Power Down Mode
The Power Down mode stops the oscillator in order to absolutely
minimize power consumption. Power Down mode is entered by
setting the PD bit in the PCON register (see Figure 22).
The processor can be made to exit Power Down mode via Reset or
one of the interrupt sources shown in Table 5. This will occur if the
interrupt is enabled and its priority is higher than any interrupt
currently in progress.
In Power Down mode, the power supply voltage may be reduced to
the RAM keep-alive voltage V
RAM
. This retains the RAM contents
at the point where Power Down mode was entered. SFR contents
are not guaranteed after V
DD
has been lowered to V
RAM
, therefore
it is recommended to wake up the processor via Reset in this case.
V
DD
must be raised to within the operating range before the Power
Down mode is exited. Since the watchdog timer has a separate
oscillator, it may reset the processor upon overflow if it is running
during Power Down.
Note that if the Brownout Detect reset is enabled, the processor will
be put into reset as soon as V
DD
drops below the brownout voltage.
If Brownout Detect is configured as an interrupt and is enabled, it will
wake up the processor from Power Down mode when V
DD
drops
below the brownout voltage.
When the processor wakes up from Power Down mode, it will start
the oscillator immediately and begin execution when the oscillator is
stable. Oscillator stability is determined by counting 1024 CPU
clocks after start-up when one of the crystal oscillator configurations
is used, or 256 clocks after start-up for the internal RC or external
clock input configurations.
Some chip functions continue to operate and draw power during
Power Down mode, increasing the total power used during Power
Down. These include the Brownout Detect, Watchdog Timer,
Comparators, and A/D converter.
BIT
PCON.7
PCON.6
SYMBOL
SMOD1
SMOD0
FUNCTION
When set, this bit doubles the UART baud rate for modes 1, 2, and 3.
This bit selects the function of bit 7 of the SCON SFR. When 0, SCON.7 is the SM0 bit. When 1,
SCON.7 is the FE (Framing Error) flag. See Figure 26 for additional information.
Brown Out Flag. Set automatically when a brownout reset or interrupt has occurred. Also set at
power on. Cleared by software. Refer to the Power Monitoring Functions section for additional
information.
Power On Flag. Set automatically when a power-on reset has occurred. Cleared by software. Refer
to the Power Monitoring Functions section for additional information.
General purpose flag 1. May be read or written by user software, but has no effect on operation.
General purpose flag 0. May be read or written by user software, but has no effect on operation.
Power Down control bit. Setting this bit activates Power Down mode operation. Cleared when the
Power Down mode is terminated (see text).
Idle mode control bit. Setting this bit activates Idle mode operation. Cleared when the Idle mode is
terminated (see text).
PCON.5
BOF
PCON.4
POF
PCON.3
PCON.2
PCON.1
GF1
GF0
PD
PCON.0
IDL
IDL
SU01168
PD
GF0
GF1
POF
BOF
SMOD0
SMOD1
0
1
2
3
4
5
6
7
PCON
Reset Value:
30h for a Power On reset
20h for a Brownout reset
00h for other reset sources
Not Bit Addressable
Address: 87h
Figure 22. Power Control Register (PCON)
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