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參數(shù)資料
| 型號(hào)： | P82B96 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Dual bi-directional bus buffer |
| 中文描述： | 雙雙向總線緩沖器 |
| 文件頁(yè)數(shù)： | 7/16頁(yè) |
| 文件大小： | 217K |
| 代理商： | P82B96 |
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Philips Semiconductors
Product data
P82B96
Dual bi-directional bus buffer
2004 Mar 26
7
SCL
SCL
SDA
SDA
P82B96
3 – 20 m CABLES
su01785
P82B96
V
CC1
+V CABLE DRIVE
V
CC
I
2
C/DDC
MASTER
GND
S
X
S
Y
R
X
T
X
R
Y
T
Y
BC
847B
470 k
4K7
I
2
C/DDC
R
X
T
X
R
Y
T
Y
V
CC
V
CC2
S
X
S
Y
GND
I
2
C/DDC
SLAVE
PC/TV RECEIVER/DECODER BOX
MONITOR/FLAT TV
VIDEO SIGNALS
R
G
B
1
BC
847B
1
470 k
+V CABLE DRIVE
Figure 4. Extending a DCC bus
Figure 4 shows how a master I
2
C-bus can be protected against
short circuits or failures in applications that involve plug/socket
connections and long cables that may become damaged. A simple
circuit is added to monitor the SDA bus and if its LOW time exceeds
the design value then the master bus is disconnected. P82B96 will
free all its I/Os if its supply is removed, so one option is to connect
its V
CC
to the output of a logic gate from, say, the 74LVC family. The
SDA and SCL lines could be timed and V
CC
disabled via the gate if
one or other lines exceeds a design value of ‘LOW’ period as in
Figure 28 of AN255 If the supply voltage of logic gates restricts the
choice of V
CC
supply then the low-cost discrete circuit in Figure 4
can be used. If the SDA line is held LOW, the 100 nF capacitor will
charge and the R
y
input will be pulled towards V
CC
. When it
exceeds V
CC
/2 the R
y
input will set the S
y
input HIGH, which in
practice means simply releasing it.
In this example the SCL line is made uni-directional by tying the R
x
pin to V
CC
. The state of the buffered SCL line cannot affect the
master clock line which is allowed when clock-stretching is not
required. It is simple to add an additional transistor or diode to
control the R
x
input in the same way as R
y
when necessary. The +V
cable drive can be any voltage up to 15 V and the bus may be run at
a lower impedance by selecting pull-up resistors for a static sink
current up to 30 mA. V
CC1
and V
CC2
may be chosen to suit the
connected devices. Because DDC uses relatively low speeds
(<100 kHz), the cable length is not restricted to 20 m by the I
2
C
signalling, but it may be limited by the video signalling.
Figure 5 shows that P82B96 can achieve high clock rates over long
cables. While calculating with lumped wiring capacitance yields
reasonable approximations to actual timing, even 25 meters of cable
is better treated using transmission line theory. Flat ribbon cables
connected as shown, with the bus signals on the outer edge, will
have a characteristic impedance in the range 100 – 200
. For
simplicity they cannot be terminated in their characteristic
impedance but a practical compromise is to use the minimum
pull-up allowed for P82B96 and place half this termination at each
end of the cable. When each pull-up is below 330
, the rising edge
waveforms have their first voltage ‘step’ level above the logic
threshold at Rx and cable timing calculations can be based on the
fast rise/fall times of resistive loading plus simple one-way
propagation delays. When the pull-up is larger, but below 750
, the
threshold at Rx will be crossed after one signal reflection. So at the
sending end it is crossed after 2 times the one-way propagation
delay and at the receiving end after 3 times that propagation delay.
For flat cables with partial plastic dielectric insulation (by using outer
cores) the one-way propagation delays will be about 5 ns/meter.
The 10% to 90% rise and fall times on the cable will be between
20 ns and 50 ns, so their delay contributions are small. There will be
ringing on falling edges that can be damped, if required, using
Schottky diodes as shown.
When the Master SCL HIGH and LOW periods can be programmed
separately, e.g. using control registers I2SCLH and I2SCLL of
89LPC932, the timings can allow for bus delays. The LOW period
should be programmed to achieve the minimum 1300 ns plus the
net delay in the slave’s response data signal caused by bus and
buffer delays. The longest data delay is the sum of the delay of the
falling edge of SCL from master to slave and the delay of the rising
edge of SDA from slave data to master. Because the buffer will
‘stretch’ the programmed SCL LOW period, the actual SCL
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P82B96_08 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual bidirectional bus buffer |
| P82B96_09 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL BIDIRECTIONAL BUS BUFFER |
| P82B96D | 功能描述:緩沖器和線路驅(qū)動(dòng)器 Dual Bidirectional Bus Buffer RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| P82B96DG4 | 功能描述:緩沖器和線路驅(qū)動(dòng)器 Dual Bidirectional Bus Buffer RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| P82B96DGKR | 功能描述:緩沖器和線路驅(qū)動(dòng)器 Dual Bidirectional Bus Buffer RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
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