Philips Semiconductors
Product data
P82B96
Dual bi-directional bus buffer
2004 Mar 26
3
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
TOPSIDE MARK
DRAWING NUMBER
8-pin plastic dual In-line package
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
P82B96PN
P82B96PN
SOT97-1
8-pin plastic small outline package
P82B96TD
P82B96T
SOT96-1
8-pin plastic thin shrink small outline package
NOTE:
1. Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging.
P82B96DP
82B96
SOT505-1
BLOCK DIAGRAM
P82B96
Sx (SDA)
Sy (SCL)
Ry (RxD, SCL)
Ty (TxD, SCL)
Rx (RxD, SDA)
Tx (TxD, SDA)
1
7
4
GND
6
5
2
3
8
+V
CC
(2–15 V)
SU01012
FUNCTIONAL DESCRIPTION
The P82B96 has two identical buffers allowing buffering of both of
the I
2
C (SDA and SCL) signals. Each buffer is made up of two logic
signal paths, a forward path from the I
2
C interface pin which drives
the buffered bus, and a reverse signal path from the buffered bus
input to drive the I
2
C-bus interface.
Thus these paths are:
1. Sense the voltage state of the I
2
C pin Sx (or Sy) and transmit
this state to the pin Tx (Ty resp.), and
2. Sense the state of the pin Rx (Ry) and pull the I
2
C pin LOW
whenever Rx (Ry) is LOW.
The rest of this discussion will address only the “x” side of the buffer:
the “y” side is identical.
The I
2
C pin (Sx) is designed to interface with a normal I
2
C-bus.
The logic threshold voltage levels on the I
2
C-bus are independent of
the IC supply V
CC
The maximum I
2
C-bus supply voltage is 15 V and
the guaranteed static sink current is 3 mA.
The logic level of Rx is determined from the power supply voltage
V
CC
of the chip. Logic LOW is below 42 % of V
CC
,
and logic HIGH is
above 58 % of V
CC
: with a typical switching threshold of half V
CC.
Tx is an open collector output without ESD protection diodes to V
CC
.
It may be connected via a pull-up resistor to a supply voltage in
excess of V
CC,
as long as the 15 V rating is not exceeded. It has a
larger current sinking capability than a normal I
2
C device, being able
to sink a static current of greater than 30 mA, and typical 100 mA
dynamic pull-down capability as well.
A logic LOW is only transmitted to Tx when the voltage at the I
2
C
pin (Sx) is below 0.6 V. A logic LOW at Rx will cause the I
2
C-bus
(Sx) to be pulled to a logic LOW level in accordance with I
2
C
requirements (max. 1.5 V in 5 V applications) but not low enough to
be looped back to the Tx output and cause the buffer to latch LOW.
The minimum LOW level this chip can achieve on the I
2
C-bus by a
LOW at Rx is typically 0.8 V.
If the supply voltage V
CC
fails, then neither the I
2
C nor the Tx output
will be held LOW. Their open collector configuration allows them to
be pulled up to the rated maximum of 15 V even without V
CC
present. The input configuration on Sx and Rx also present no
loading of external signals even when V
CC
is not present.
The effective input capacitance of any signal pin, measured by its
effect on bus rise times, is less than 7 pF for all bus voltages and
supply voltages including V
CC
= 0 V.