參數(shù)資料
型號： P82B96
廠商： NXP Semiconductors N.V.
英文描述： Dual bi-directional bus buffer
中文描述： 雙雙向總線緩沖器
文件頁數(shù)： 5/16頁
文件大小： 217K
代理商： P82B96
Philips Semiconductors
Product data
P82B96
Dual bi-directional bus buffer
2004 Mar 26
5
—
0.5
UNIT
600
MAX.
TYP.
á
0.58
MIN.
Fraction of applied V
CC
CONDITIONS
á
áááááááááááááááááááááááááááááá
V
Rx
, V
Ry
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á
áááááááááááááááááááááááááááááá
NOTES:
1. The minimum value requirement for pull-up current, 200
μ
A, guarantees that the minimum value for V
SX
output LOW will always exceed the
minimum V
SX
input HIGH level to eliminate any possibility of latching. The specified difference is guaranteed by design within any IC. While
the tolerances on absolute levels allow a small probability the LOW from one S
X
output is recognized by an S
X
input of another P82B96 this
has no consequences for normal applications. In any design the S
X
pins of different ICs should never be linked because the resulting system
would be very susceptible to induced noise and would not support all I
2
C operating modes.
2. The output logic LOW depends on the sink current. For scaling, see Application Note AN255
3. The input logic threshold is independent of the supply voltage.
PARAMETER
ááááááááááááááááááááááááááááááá
V
Sx
, V
Sy
Sx
Sy
dV
Sx
dV
/dT
V
, V
SYMBOL
áááááááááááááááááááááááááááááááááá
V
Rx
, V
Ry
Fraction of applied V
CC
Logic level threshold difference
Input logic switching threshold voltages
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ááá
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áááááááááááááááááááááááááááááááááá
ááá
Input logic voltage LOW (Note 3)
On normal I
2
C-bus
—
640
áááááá
—
V
0.42
mV
áááááááá
Fraction of applied V
áááá
á
Input logic HIGH level
ááááááááá
á
—
ááááááááááá
áá
á
á
—
–2
á
á
V
áá
á
—
—
V
V
Sx
Sy
á
ááááááááá
á
V
input HIGH max
áááááááá
SX
á
áá
á
85
á
á
á
áá
á
CHARACTERISTICS
At T
amb
= 25
°
CC
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á
ááááá
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á
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á
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áááá
á
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NOTES ON RESPONSE TIME
The fall-time of V
TX
from 5 V to 2.5 V in the test is approximately 15 ns.
The fall-time of V
SX
from 5 V to 2.5 V in the test is approximately 50 ns.
The rise-time of V
TX
from 0 V to 2.5 V in the test is approximately 20 ns.
The rise-time of V
SX
from 0.9 V to 2.5 V in the test is approximately 70 ns.
CC
V
Sx
Sy
V
Tx
, V
Ty
dV/dT
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ááááááááááááááááááááááááááááááá
ááá
áááááááááááááááááááááááááááááááááá
V
to V
V
Sy
to V
Ty
Tx
output falling 50%.
R
Tx
pull-up = 160
,
no capacitive load, V
= 5 V
á
áááááááááááááááááá
CC
voltage at which all buses are
á
áááááá
á
áá
—
á
áá
–4
á
á
á
áá
mV/K
á
—
á
á
á
T
fall delay
V
= input switching threshold,
áááááááááá
ááá
Rx
to V
Sx
V
Ry
to V
Sy
Sx
output falling 50%.
á
á
á
no capacitive load, V
= 5 V
áááááá
á
áááááááááááá
R
Tx
pull-up = 160
,
áá
áá
áá
á
áá
á
áá
áá
áá
áá
áá
á
á
á
áá
áá
áá
á
á
á
á
áááááááááá
output reaching 50% V
T
rise delay
V
Sx
V
Sy
to V
Ty
áááááááááá
V
to V
á
á
V
Sx
and V
Tx
output reaching 50% V
CC
á
á
á
á
á
—
á
á
á
90
á
á
á
á
á
áá
—
á
á
á
ns
á
Rx
áááááááááá
áááááááááá
R
Sx
pull-up = 1500
, no
capacitive load, V
CC
= 5 V
—
áá
250
—
áá
ns
á
T
V
Rx
to V
Sx
á
Rx
á
no capacitive load, V
CC
= 5 V
á
á
á
á
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