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參數(shù)資料
| 型號： | P82B96 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Dual bi-directional bus buffer |
| 中文描述： | 雙雙向總線緩沖器 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 217K |
| 代理商： | P82B96 |
Philips Semiconductors
Product data
P82B96
Dual bi-directional bus buffer
2004 Mar 26
10
Cm = MASTER BUS
CAPACITANCE
Cb = BUFFERED BUS
WIRING CAPACITANCE
Cs = SLAVE BUS
CAPACITANCE
MASTER
I
2
C
I
2
C
SLAVE
P82B96
P82B96
V
CCM
SDA
Rm
Rb
Rs
V
CCS
SDA
Sx
Tx/Rx
Tx/Rx
Sx
GND/0 V
C)
RISING EDGE OF SDA AT SLAVE IS DELAYED BY THE BUFFERS AND BUS RISE TIMES
EFFECTIVE DELAY OF SDA AT MASTER = 270 + 0.2RsCs + 0.7 (RbCb + RmCm) (ns),
C = F,
R =
LOCAL MASTER BUS
BUFFERED EXPANSION BUS
REMOTE SLAVE BUS
su01789
V
CCB
Figure 8.
Figures 6, 7, and 8 show the P82B96 used to drive extended bus
wiring, with relatively large capacitance, linking two Fast mode
I
2
C-bus nodes. It includes simplified expressions for making the
relevant timing calculations for 3.3/5 V operation. Because the
buffers and the wiring introduce timing delays, it may be necessary
to decrease the nominal SCL frequency below 400 kHz. In most
cases the actual bus frequency will be lower than the nominal
Master timing due to bit-wise stretching of the clock periods.
The delay factors involved in calculation of the allowed bus speed
are:
A) The propagation delay of the Master signal through the buffers
and wiring to the Slave. The important delay is that of the falling
edge of SCL because this edge ‘requests’ the data or
Acknowledge from a Slave.
B) The effective stretching of the nominal LOW period of SCL at the
Master caused by the buffer and bus rise times
C) The propagation delay of the Slave’s response signal through the
buffers and wiring back to the Master. The important delay is
that of a rising edge in the SDA signal. Rising edges are always
slower and are therefore delayed by a longer time than falling
edges. (The rising edges are limited by the passive pull-up while
falling edges are actively driven)
The timing requirement in any I
2
C system is that a Slave’s data
response (which is provided in response to a falling edge of SCL)
must be received at the Master before the end of the corresponding
low period of SCL as appears on the bus wiring at the Master. Since
all Slaves will, as a minimum, satisfy the worst case timing
requirements of a 400 kHz part, they must provide their response
within the minimum allowed clock LOW period of 1300 ns. Therefore
in systems that introduce additional delays it is only necessary to
extend that minimum clock low period by any “effective” delay of the
Slave’s response. The effective delay of the slaves response = total
delays in SCL falling edge from the Master reaching the Slave (A) –
the effective delay (stretch) of the SCL rising edge (B) + total delays
in the Slave’s response data, carried on SDA, reaching the
Master (C).
The Master microcontroller should be programmed to produce a
nominal SCL LOW period = (1300 + A – B + C) ns, and should be
programmed to produce the nominal minimum SCL HIGH period of
600 ns. Then a check should be made to ensure the cycle time is
not shorter than the minimum 2500 ns. If found necessary, just
increase either clock period.
Due to clock stretching, the SCL cycle time will always be longer
than (600 + 1300 + A + C) ns.
Example:
The Master bus has an RmCm product of 100 ns and V
CCM
= 5 V.
The buffered bus has a capacitance of 1 nF and a pull-up resistor of
160 ohms to 5 V giving an RbCb product of 160 ns. The Slave bus
also has an RsCs product of 100 ns.
The microcontroller LOW period should be programmed to
≥
(1300 + 372.5 – 482 + 472) ns, that is
≥
1662.5 ns.
Its HIGH period may be programmed to the minimum 600 ns.
The nominal microcontroller clock period will be
≥
(1662.5 + 600) ns = 2262.5 ns, equivalent to a frequency of
442 kHz.
The actual bus clock period, including the 482 ns clock stretch
effect, will be below (nominal + stretch) = (2262.5 + 482) ns or
≥
2745 ns, equivalent to an allowable frequency of 364 kHz.
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| P82B96_08 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual bidirectional bus buffer |
| P82B96_09 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL BIDIRECTIONAL BUS BUFFER |
| P82B96D | 功能描述:緩沖器和線路驅(qū)動器 Dual Bidirectional Bus Buffer RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| P82B96DG4 | 功能描述:緩沖器和線路驅(qū)動器 Dual Bidirectional Bus Buffer RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| P82B96DGKR | 功能描述:緩沖器和線路驅(qū)動器 Dual Bidirectional Bus Buffer RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
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