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參數(shù)資料
| 型號： | P4C1981-45CMB |
| 廠商： | PYRAMID SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 16K X 4 STANDARD SRAM, 45 ns, CDIP28 |
| 封裝： | 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-28 |
| 文件頁數(shù)： | 5/13頁 |
| 文件大?。?/td> | 294K |
| 代理商： | P4C1981-45CMB |
1
Document # SRAM114 REV B
Revised August 2006
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25 ns (Commercial)
– 12/15/20/25/35 ns (Industrial)
– 15/20/25/35/45 ns (Military)
Low Power Operation (Commercial/Military)
Output Enable and Dual Chip Enable Functions
5V ± 10% Power Supply
Data Retention with 2.0V Supply, 10 A Typical
Current (P4C1981L/1982L Military)
Separate Inputs and Outputs
– P4C1981/L Input Data at Outputs during Write
– P4C1982/L Outputs in High Z during Write
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
– 28-Pin 300 mil DIP, SOJ
– 28-Pin 350 x 550 mil LCC
– 28-Pin CERPACK
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
The P4C1981/L and P4C1982/L are 65,536-bit (16Kx4)
ultra high-speed static RAMs similar to the P4C198, but
with separate data I/O pins. The P4C1981/L feature a
transparent write operation when OE is low; the outputs
of the P4C1982/L are in high impedance during the write
cycle. All devices have low power standby modes. The
RAMs operate from a single 5V ± 10% tolerance power
supply. With battery backup, data integrity is maintained
for supply voltages down to 2.0V. Current drain is
typically 10 A from 2.0V supply.
DESCRIPTION
Access times as fast as 10 nanoseconds are available,
permitting greatly enhanced system operating speeds.
CMOS is used to reduce power consumption. For the
P4C1982L and P4C1981L, power is only 5.5 mW standby
with CMOS input levels.
TheP4C1981/LandP4C1982/Lareavailablein28-pin300
mil DIP and SOJ, 28-pin 350x550 mil LCC and a 28-pin
CERPACK package providing excellent board level den-
sities.
DIP (P5, C5, D5-2), SOJ (J5)
CERPACK (F4) SIMILAR
LCC (L5)
P4C1981/P4C1981L, P4C1982/P4C1982L
ULTRA HIGH SPEED 16K x 4
CMOS STATIC RAMS
P4C1981/ 1982
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