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參數(shù)資料
| 型號： | P4C1981-45CMB |
| 廠商： | PYRAMID SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 16K X 4 STANDARD SRAM, 45 ns, CDIP28 |
| 封裝： | 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-28 |
| 文件頁數(shù)： | 10/13頁 |
| 文件大小： | 294K |
| 代理商： | P4C1981-45CMB |
P4C1981/1981L, P4C1982/1982L
Page 8 of 13
Document # SRAM114 REV B
TRUTH TABLE
P4C1981/L (P4C1982/L)
CE
1
H
X
L
CE
2
X
H
L
WE
X
H
L
OE
X
H
L
H
L
Mode
Standby
Output Inhibit
READ
WRITE
Output
High Z
D
OUT
High Z
D
IN (High Z)
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
3ns
Input Timing Reference Level
1.5V
Output Timing Reference Level
1.5V
Output Load
See Figures 1 and 2
AC TEST CONDITIONS
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P4C1981/L and P4C1982/L, care
must be taken when testing this device; an inadequate setup can cause
a normal functioning part to be rejected as faulty. Long high-inductance
leads that cause supply bounce must be avoided by bringing the V
CC and
ground planes directly up to the contactor fingers. A 0.01 F high
Figure 1. Output Load
Figure 2. Thevenin Equivalent
frequency capacitor is also required between V
CC and ground. To avoid
signal reflections, proper termination must be used; for example, a 50
test environment should be terminated into a 50
load with 1.73V
(Thevenin Voltage) at the comparator input, and a 116
resistor must
be used in series with D
OUT to match 166 (Thevenin Resistance).
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