參數(shù)資料
型號(hào): P4C1981-45CMB
廠商: PYRAMID SEMICONDUCTOR CORP
元件分類(lèi): SRAM
英文描述: 16K X 4 STANDARD SRAM, 45 ns, CDIP28
封裝: 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-28
文件頁(yè)數(shù): 11/13頁(yè)
文件大?。?/td> 294K
代理商: P4C1981-45CMB
P4C1981/1981L, P4C1982/1982L
Page 7 of 13
Document # SRAM114 REV B
WRITE CYCLE NO. 2 (WE
WE
WE CONTROLLED)(13,14)
1520 08
WRITE CYCLE NO. 3 (CE
CE
1, CE
CE
2 CONTROLLED)
(11,12)
Notes:
12. CE (CE
1, CE2) and WE must be LOW for WRITE cycle.
13. OE is LOW for WRITE cycle.
14. If CE
1 or CE2 goes HIGH simultaneously with WE HIGH, the
output remains in a high impedance state.
15. Write Cycle Time is measured from the last valid address to the
first transitioning address.
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