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參數(shù)資料
| 型號(hào)： | P4C169-55LMB |
| 廠商： | PYRAMID SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 4K X 4 STANDARD SRAM, 55 ns, CQCC20 |
| 封裝： | 0.290 X 0.430 INCH, CERAMIC, LCC-20 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 263K |
| 代理商： | P4C169-55LMB |
P4C168, P4C169, P4C170
4
Notes:
7. ADDRESS must be valid prior to, or coincident with CE/CS transition
low. For Fast CS, t
AA must still be met.
8. Transition is measured ±200mV from steady state voltage prior to
change, with loading as specified in Figure 1.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
TIMING WAVEFORM OF READ CYCLE NO. 2 (
CE
CE/CS
CS
CS CONTROLLED)(5,7)
TIMING WAVEFORM OF READ CYCLE NO. 3—P4C170 ONLY (
OE
OE CONTROLLED)(5)
TIMING WAVEFORM OF READ CYCLE NO. 1 (ADDRESS CONTROLLED)(5,6)
Notes:
5. WE is HIGH for READ cycle.
6. CE/CS and OE are LOW for READ cycle.
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