參數(shù)資料
型號(hào): P4C169-55LMB
廠商: PYRAMID SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 4K X 4 STANDARD SRAM, 55 ns, CQCC20
封裝: 0.290 X 0.430 INCH, CERAMIC, LCC-20
文件頁(yè)數(shù): 11/14頁(yè)
文件大小: 263K
代理商: P4C169-55LMB
P4C168, P4C169, P4C170
6
Mode
CE
CE (CS
CS
CS)
WE
Output
Standby (Deselect)
H
X
High Z
Read
L
H
D
OUT
Write
L
High Z
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CE
CE/CS
CS
CS CONTROLLED)(10)
TRUTH TABLES
P4C168 (P4C169)
P4C170
Mode
CE
WE
OE
Output
Deselect
H
X
High Z
Read
L
H
L
D
OUT
Output Inhibit
L
H
High Z
Write
L
X
High Z
Notes:
10. CE/CS and WE must be LOW for WRITE cycle.
11. If CE/CS goes HIGH simultaneously with WE HIGH, the output
remains in a high impedance state.
12. Write Cycle Time is measured from the last valid address to the first
transitioning address.
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
WE
WE CONTROLLED)(10)
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