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參數(shù)資料
| 型號(hào)： | OX16C954 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | High Performance Quad UART with 128-byte FIFOs Intel / Motorola Bus Interface |
| 中文描述： | UART的高性能四路128字節(jié)的FIFO英特爾/摩托羅拉總線接口 |
| 文件頁數(shù)： | 24/54頁 |
| 文件大?。?/td> | 529K |
| 代理商： | OX16C954 |
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Data Sheet Revision 1.0
Page 24
OX16C954 rev B
OXFORD SEMICONDUCTOR LTD.
450, 550 and extended 550 modes:
The transmtter interrupt trigger levels are set to 1 and
FCR[5:4] are ignored.
650 mode:
In 650 mode the transmtter interrupt trigger levels can be
set to the following values:
FCR[5:4]
Transmit Interrupt Trigger level
00
01
10
11
16
32
64
112
Table 9: Transmit Interrupt Trigger Levels
These levels only apply when in Enhanced mode and in
DMA mode 1(FCR[3] = 1), otherwise the trigger level is set
to 1. A transmtter empty interrupt will be generated (if
enabled) if the TFL falls below the trigger level.
750 Mode:
In 750 compatible non-enhanced (EFR[4] = 0) mode,
transmtter trigger level is set to 1, FCR[4] is unused and
FCR[5] defines the FIFO depth as follows:
FCR[5]=0 Transmtter and receiver FIFO size is 16 bytes.
FCR[5]=1 Transmtter and receiver FIFO size is 128 bytes.
In non-Enhanced mode and when FIFOSEL#pin is high,
FCR[5] is writable only when LCR[7] is set. Note that in
Enhanced mode, the FIFO size is increased to 128 bytes
when FCR[0] is set.
9 L
INE
C
ONTROL
& S
TATUS
950 mode:
Setting ACR[5]=1 enables 950-mode trigger levels set
using the TTL register (see section 15.4), FCR[5:4] are
ignored.
FCR[7:6]: RHR trigger level
In 550,
450, 550, extended 550, 650 and 750 modes:
The receiver FIFO trigger levels are defined using
FCR[7:6]. The interrupt trigger level and upper flow control
trigger level where appropriate are defined by L1 in the
table below. L2 defines the lower flow control trigger level.
Separate upper and lower flow control trigger levels
introduce a hysteresis element in in-band and out-of-band
flow control (see section 13). In Byte mode (450 mode) the
trigger levels are all set to 1.
FCR
Mode
550
FIFO Size 16
L1
1
4
8
14
Ext. 550 / 750
FIFO Size 128
L1
1
32
64
112
650
FIFO Size 128
L1
16
32
112
120
L2
n/a
n/a
n/a
n/a
L2
1
1
1
1
L2
1
16
32
112
00
01
10
11
Table 10: Compatible Receiver Trigger Levels
950 mode:
In simlar fashion to for transmtter trigger levels, setting
ACR[5]=1 enables 950-mode receiver trigger levels.
FCR[7:6] are ignored.
A receiver data interrupt will be generated (if enabled) if the
Receiver FIFO Level (‘RFL’) reaches the upper trigger
level.
9.1
On the falling edge of a start bit, the receiver will wait for
1/2 bit and re-synchronise the receivers sampling clock
onto the centre of the start bit. The start bit is valid if the
SIN line is still low at this md-bit sample and the receiver
will proceed to read in a data character. Verifying the start
bit prevents noise generating spurious character
generation.
Once the first stop bit has been sampled, the received data
is transferred to the RHR and the receiver will then wait for
a low transition on SIN (signifying the next start bit).
The receiver will continue receiving data even if the RHR is
full or the receiver has been disabled (see section 15.3) in
order to maintain framng synchronisation. The only
False Start Bit Detection
difference is that the received data does not get transferred
to the RHR.
9.2
The LCR specifies the data format that is common to both
transmtter and receiver. Writing 0xBF to LCR enables
access to the EFR, XON1, XOFF1, XON2 and XOFF2,
DLL and DLMregisters. This value (0xBF) corresponds to
an unused data format. Writing the value 0xBF to LCR will
set LCR[7] but leaves LCR[6:0] unchanged. Therefore, the
data format of the transmtter and receiver data is not
affected. Write the desired LCR value to exit fromthis
selection.
Line Control Register ‘LCR’
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