參數(shù)資料
型號(hào)： OX16C954
廠商： Electronic Theatre Controls, Inc.
英文描述： High Performance Quad UART with 128-byte FIFOs Intel / Motorola Bus Interface
中文描述： UART的高性能四路128字節(jié)的FIFO英特爾/摩托羅拉總線接口
文件頁(yè)數(shù)： 12/54頁(yè)
文件大?。?/td> 529K
代理商： OX16C954
Data Sheet Revision 1.0
Page 12
OX16C954 rev B
OXFORD SEMICONDUCTOR LTD.
TQFP
Serial Port Pins Contd.
79
62
39
22
79
62
39
22
10
PLCC
Dir
1
Name
Description
60
44
26
10
60
44
26
I
I
I
I
I
I
I
I
DSR[3]#
DSR[2]#
DSR[1]#
DSR[0]#
RxClkIn[3]
RxClkIn[2]
RxClkIn[1]
RxClkIn[0]
DCD[3]#
DCD[2]#
DCD[1]#
DCD[0]#
RI[3]#
RI[2]#
RI[1]#
RI[0]#
Ext_CK[3]
Ext_CK[2]
Ext_CK[1]
Ext_CK[0]
Active-low modem“data-set-ready” input, for each uart respectively.
If automated DSR#flow control is enabled for the corresponding UART
channel, upon deassertion of the channel’s DSR#pin, the transmtter will
complete the current character and enter the idle mode until the DSR#pin
is reasserted. Note: flow control characters are transmtted regardless of
the state of the DSR#pin. The state of this pin is reflected in bit 5 of the
MSR.
It can also be used as a general-purpose input
.
External receiver clock for isochronous applications for each uart
respectively. Selected when CKS[1:0] = ‘01’.
2
59
42
19
61
43
27
9
I
I
I
I
Active-low modemData-Carrier-Detect input, for each uart respectively.
The state of this pin is reflected in bit 7 of the MSR.
It can also be used
as a general-purpose input
.
3
58
43
18
3
58
43
18
62
42
28
8
62
42
28
8
I
I
I
I
I
I
I
I
Active-low modemRing-Indicator input, for each uart respectively.
The state of this pin is reflected in bit 6 of the MSR.
It can also be used
as a general-purpose input
. RI can be configured as tx and rx for a 1x
clock in isochronous operation.
External transmtter clock for each uart respectively. This clock can be
used by the transmtter (and by the receiver indirectly) when CKS[6] = ‘1’.
Interrupt & DMA Pins
1
61
41
21
No pin
No pin
No pin
No pin
O
O
O
O
TXRDY3#
TXRDY2#
TXRDY1#
TXRDY0#
Signal for the DMA transfer of transmtter data, for Uart 3.
Signal for the DMA transfer of transmtter data, for Uart 2.
Signal for the DMA transfer of transmtter data, for Uart 1.
Signal for the DMA transfer of transmtter data, for Uart 0.
There are two modes of DMA signalling described in section 8.1
Signal for the DMA transfer of transmtter data.
This pin is the wire ”O(jiān)R-ed” function of the TXRDY#signals of all
channels.
Signal for the DMA transfer of receiver data, for Uart 3.
Signal for the DMA transfer of receiver data, for Uart 2.
Signal for the DMA transfer of receiver data, for Uart 1.
Signal for the DMA transfer of receiver data, for Uart 0.
There are two modes of DMA signalling described in section 8.1
Signal for DMA transfer of received data.
This pin is the wire ”O(jiān)R-ed” function of the RXRDY#signals of all
channels.
55
39
O
TXRDY#
80
60
40
20
No pin
No pin
No pin
No pin
O
O
O
O
RXRDY3#
RXRDY2#
RXRDY1#
RXRDY0#
54
38
O
RXRDY#
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