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參數(shù)資料
| 型號： | OX16C954 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | High Performance Quad UART with 128-byte FIFOs Intel / Motorola Bus Interface |
| 中文描述： | UART的高性能四路128字節(jié)的FIFO英特爾/摩托羅拉總線接口 |
| 文件頁數(shù)： | 23/54頁 |
| 文件大?。?/td> | 529K |
| 代理商： | OX16C954 |
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Data Sheet Revision 1.0
Page 23
OX16C954 rev B
OXFORD SEMICONDUCTOR LTD.
8 T
RANSMITTER AND RECEIVER
FIFO
S
Both the transmtter and receiver have associated holding
registers (FIFOs), referred to as the transmtter holding
register (THR) and receiver holding register (RHR)
respectively.
In normal operation, when the transmtter finishes
transmtting a byte it will remove the next data fromthe top
of the THR and proceed to transmt it. If the THR is empty,
it will wait until data is written into it. If THR is empty and
the last character being transmtted has been completed
(i.e. the transmtter shift register is empty) the transmtter is
said to be idle. Simlarly, when the receiver finishes
receiving a byte, it will transfer it to the bottomof the RHR.
If the RHR is full, an overrun condition will occur (see
section 9.3).
Data is written into the bottomof the THR queue and read
fromthe top of the RHR queue completely asynchronously
to the operation of the transmtter and receiver.
The size of the FIFOs is dependent on the setting of the
FCR register. When in Byte mode, these FIFOs only
accept one byte at a time before indicating that they are
full; this is compatible with the 16C450. When in a FIFO
mode, the size of the FIFOs is either 16 (compatible with
the 16C550) or 128.
Data written to the THR when it is full is lost. Data read
fromthe RHR when it is empty is invalid. The empty or full
status of the FIFOs are indicated in the Line Status
Register ‘LSR’ (see section 9.3). Interrupts are generated
when the UART is ready for data transfer to/fromthe
FIFOs. The number of items in each FIFO may also be
read back fromthe transmtter FIFO level (TFL) and
receiver FIFO level (RFL) registers (see section 15.2).
8.1
FCR[0]: Enable FIFO mode
logic 0
Byte mode.
logic 1
FIFO mode.
This bit should be enabled before setting the FIFO trigger
levels.
FCR[1]: Flush RHR
logic 0
No change.
logic 1
Flushes the contents of the RHR
This is only operative when already in a FIFO mode. The
RHR is automatically flushed whenever changing between
Byte mode and a FIFO mode. This bit will return to zero
after clearing the FIFOs.
FIFO Control Register ‘FCR’
FCR[2]: Flush THR
logic 0
No change.
logic 1
Flushes the contents of the THR, in the same
manner as FCR[1] does for the RHR.
DMA Transfer Signalling:
FCR[3]: DMA signalling mode / Tx trigger level enable
logic 0
DMA mode '0'.
logic 1
DMA mode '1'.
Note: In DMA mode 0, the transmitter trigger level is
ALWAYS set to 1, thus ignoring FCR[5:4] and TTL.
DMA Control signals can be generated using the TXRDY#
and RXRDY#pins. Their operation is defined as follows:
The TXRDY#pin has no hysteresis and is simply activated
using a comparison operation. When the UART is in DMA
mode 0 (or in Byte mode), the TXRDY#output pin is active
(low) whenever any channels transmt FIFO (THR) is
empty, otherwise it is inactive.
When in DMA mode 1, the TXRDY#pin is inactive (high)
when every channels transmt FIFO is full, otherwise it is
active, signifying that one or more channels have roomin
their transmt FIFOs.
The RXRDY#pin can operate with hysteresis. In DMA
mode 0 (or in Byte mode), RXRDY#is only active (low)
when one or more channels have data in their receiver
FIFO. It is inactive therefore, when all channels receiver
FIFOs are empty.
When in DMA mode 1, RXRDY#operates as follows:
1. RXRDY#is set active when any channels receiver
FIFO fill level has reached the receiver interrupt
trigger level for that channel, or a time-out event has
occurred (see section 10.3). It remains active until
condition 2 (defined below) is met.
2. RXRDY#is set inactive when every channels receiver
has been emptied. It remains in this state until
condition 1 (defined above) occurs again.
Note for the 80 pin TQFP package, individual channel
TXRDY# RXRDY#signals are also generated.
FCR[5:4]: THR trigger level
Generally in 450, 550, extended 550 and 950 modes these
bits are unused (see section 5 for mode definition). In 650
mode they define the transmtter interrupt trigger levels and
in 750 mode FCR[5] increase the FIFO size.
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