參數(shù)資料
型號： ORT8850L-2BM680I
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 68/105頁
文件大小： 0K
描述： IC FPSC TRANSCEIVER 8CH 680-BGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標準包裝： 24
系列： *
Lattice Semiconductor
ORCA ORT8850 Data Sheet
65
30027*
0303F
30057
3006F
30087
3009F
300B7
300CF
[0]
R/W
enable channel
alarm
0
Channel alarm bit (30026, ...) enable. Set to 1 to enable
alarm bit to propagate to alarm 0x30010
[1]
R/W
enable AIS-P ag
0
AIS -P ag alarm enable. Set to 1 to enable alarm bit to
propagate to alarm 0x30010
[2]
enable pointer
mover elastic
store overow
ag
0
Pointer mover elastic store overow ag enable. Set to 1 to
enable alarm bit to propagate to 0x30010
[3-7]
-
Not Used
0
30028*
30040
30058
30070
30088
300A0
300B8
300D0
[0]
R
FIFO aligner
threshold error
ag
00
Alarm is set to 1 if either the min or max FIFO threshold
levels are violated, the min and max threshold levels can
be set in address 0x3000A and 0x300B. Alarm enable is
0x30029 bit 0. Write 1 to clear this alarm bit This alarm is
only valid when FIFO OOS ag is also set.
[1]
RX internal path
parity error ag
Alarm indicator on receive path internal parity error. Alarm
is enabled in 0x30029 bit 1. Write 1 to clear
[2]
OOF ag
Alarm indicator channel is OOF. Alarm enable is 0x30029
bit 2. Write 1 to clear.
[3]
LVDS link B1 par-
ity error ag
Alarm indicator that channel has found a B1 parity error.
Alarm enable is 0x30029 bit 3. Write 1 to clear.
[4]
DINxx parallel
bus parity error
ag
0
Alarm indicator channel has found a parity error on the
DINxx input from the FPGA.Alarm enable is 0x30029 bit 4.
Write 1 to clear.
[5]
TOH serial input
port parity error
ag
0
Alarm indicator channel has found a parity error on the
TOH_INxx input from the FPGA. Write 1 to clear this
alarm. Alarm enable is 0x30028 bit 5.
[6]
FIFO OOS error
ag
0
Alarm indicates channel group is out of sync. Write 1 to
clear. Alarm enable is 0x30028.
[7]
-
Not Used
0
30029*
30041
30059
30071
30089
300A1
300B9
300D1
[0:6]
R/W
channel alarm
enable
00
Enable bits for channel alarm register 0x30028. Set to 1 to
enable and to propagate the alarm to register 0x30026 bit
0.
[7]
-
Not Used
0
3002A*
30042
3005A
30072
3008A
300A2
300BA
300D2
[0:3]
R
AIS alarm ags 3,
6, 9, 12
0
These are the AIS-P alarm ags. 1 if the LVDS input STS #
contains AIS.
[4-7]
-
Not Used
0
Table 19. Memory Map Descriptions (Continued)
(0x)
Absolute
Address
Bit
Type
Name
Reset
Value
(0x)
Description
相關(guān)PDF資料
PDF描述
ORT8850H-1BM680C IC FPSC TRANSCEIVER 8CH 680-BGA
ORT82G5-2F680I IC FPSC TRANSCEIVER 8CH 680-BGA
ORT82G5-2F680C IC FPSC TRANSCEIVER 8CH 680-BGA
D38999/26JC8PN CONN PLUG 8POS STRAIGHT W/PINS
MS27467T25F61SC CONN PLUG 61POS STRAIGHT W/SCKT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORT8850L-2BMN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850L-2BMN680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850L-3BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850L-3BMN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT9303 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*