參數(shù)資料
型號(hào)： ORT8850L-2BM680I
廠商： Lattice Semiconductor Corporation
文件頁(yè)數(shù)： 65/105頁(yè)
文件大?。?/td> 0K
描述： IC FPSC TRANSCEIVER 8CH 680-BGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 24
系列： *
Lattice Semiconductor
ORCA ORT8850 Data Sheet
62
30017
[0]
R/W
BD resync
0
Channel BD alignment FIFO resync. Write “1” to resync
this channel. When no alignment is used, this resets the
read pointer to the middle of the FIFO. Write “0” for normal
operation
[1]
R/W
BC resync
0
Channel BC alignment FIFO resync. Write “1” to resync
this channel. When no alignment is used, this resets the
read pointer to the middle of the FIFO. Write “0” for normal
operation
[2]
R/W
BB resync
0
Channel BB alignment FIFO resync. Write “1” to resync
this channel. When no alignment is used, this resets the
read pointer to the middle of the FIFO. Write “0” for normal
operation
[3]
R/W
BA resync
0
Channel BA alignment FIFO resync. Write “1” to resync
this channel. When no alignment is used, this resets the
read pointer to the middle of the FIFO. Write “0” for normal
operation
[4]
R/W
AD resync
0
Channel AD alignment FIFO resync. Write “1” to resync
this channel. When no alignment is used, this resets the
read pointer to the middle of the FIFO.Write “0” for normal
operation
[5]
R/W
AC resync
0
Channel AC alignment FIFO resync. Write “1” to resync
this channel. When no alignment is used, this resets the
read pointer to the middle of the FIFO.Write “0” for normal
operation
[6]
R/W
AB resync
0
Channel AB alignment FIFO resync. Write “1” to resync
this channel. When no alignment is used, this resets the
read pointer to the middle of the FIFO.Write “0” for normal
operation
[7]
R/W
AA resync
0
Channel AA alignment FIFO resync. Write “1” to resync
this channel. When no alignment is used, this resets the
read pointer to the middle of the FIFO.Write “0” for normal
operation
30018
[0]
R/W
AD/BD resync
0
2-link AD/BD alignment FIFO resync.
Write “1” to resync this link. Write “0” for normal operation.
[1]
R/W
AC/BC resync
0
2-link AC/BC alignment FIFO resync.
Write “1” to resync this link. Write “0” for normal operation.
[2]
R/W
AB/BB resync
0
2-link AB/BB alignment FIFO resync.
Write “1” to resync this link. Write “0” for normal operation.
[3]
R/W
AA/BA resync
0
2-link AA/BA alignment FIFO resync.
Write “1” to resync this link. Write “0” for normal operation.
[4]
R/W
STM B resync
0
Quad B alignment resync. Write “0” for normal operation.
[5]
R/W
STM A resync
0
Quad A alignment FIFO resync
Write “0” for normal operation.
[6]
R/W
All 8 resync
0
All 8 channel alignment FIFO resync.
Write “0” for normal operation.
[7]
-
Not Used
N/A
Table 19. Memory Map Descriptions (Continued)
(0x)
Absolute
Address
Bit
Type
Name
Reset
Value
(0x)
Description
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參數(shù)描述
ORT8850L-2BMN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850L-2BMN680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850L-3BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850L-3BMN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT9303 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY
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