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參數(shù)資料
| 型號(hào)： | ORT8850L-2BM680I |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 51/105頁 |
| 文件大小： | 0K |
| 描述： | IC FPSC TRANSCEIVER 8CH 680-BGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORT8850 Data Sheet
5
New 200 MHz embedded quad-port RAM blocks, two read ports, two write ports, and two sets of byte lane
enables. Each embedded RAM block can be congured as:
– One—512 x 18 (quad-port, two read/two write) with optional built-in arbitration.
– One—256 x 36 (dual-port, one read/one write).
– One—1K x 9 (dual-port, one read/one write).
– Two—512 x 9 (dual-port, one read/one write for each).
– Two RAM with arbitrary number of words whose sum is 512 or less by 18 (dual-port, one read/one write).
– Supports joining of RAM blocks.
– Two 16 x 8-bit Content Addressable Memory (CAM) support.
– FIFO 512 x 18, 256 x 36, 1K x 9, or dual 512 x 9.
– Constant multiply (8 x 16 or 16 x 8).
– Dual variable multiply (8 x 8).
Embedded 32-bit internal system bus plus 4-bit parity interconnects FPGA logic, MicroProcessor Interface (MPI),
embedded RAM blocks, and embedded backplane transceiver blocks with 100 MHz bus performance. Included
are built-in system registers that act as the control and status center for the device.
Built-in testability:
– Full boundary scan (
IEEE 1149.1 and Draft 1149.2 JTAG).
– Programming and readback through boundary scan port compliant to
IEEE Draft 1532:D1.7.
– TS_ALL testability function to 3-state all I/O pins.
– New temperature-sensing diode.
Cycle stealing capability allows a typical 15% to 40% internal speed improvement after nal place and route. This
feature also supports compliance with many setup/hold and clock to out I/O specications and may provide
reduced ground bounce for output buses by allowing exible delays of switching output buffers.
Programmable Logic System Features
PCI local bus compliant for FPGA I/Os.
Improved
PowerPC/Power QUICC MPC860 and PowerPC II MPC8260 high-speed synchronous MicroProcessor
Interface can be used for conguration, readback, device control, and device status, as well as for a general-pur-
pose interface to the FPGA logic, RAMs, and embedded backplane transceiver blocks. Glueless interface to syn-
chronous
PowerPC processors with user-congurable address space provided.
New embedded
AMBA specication 2.0 AHB system bus (ARM
processor) facilitates communication among
the MicroProcessor Interface, conguration logic, embedded block RAM, FPGA logic, and backplane transceiver
logic.
New network PLLs meet ITU-T G.811 specications and provide clock conditioning for DS-1/E-1 and STS-
3/STM-1 applications.
Variable size bused readback of conguration data capability with the built-in MicroProcessor Interface and sys-
tem bus.
Internal, 3-state, and bidirectional buses with simple control provided by the SLIC.
New clock routing structures for global and local clocking signicantly increases speed and reduces skew (<200
ps for OR4E04).
New local clock routing structures allow creation of localized clock trees.
Two new edge clock routing structures allow up to six high-speed clocks on each edge of the device for improved
setup/hold and clock-to-out performance.
New Double-Data Rate (DDR) and Zero-Bus Turn-around (ZBT) memory interfaces support the latest high-
speed memory interfaces.
New 2x/4x uplink and downlink I/O capabilities interface high-speed external I/Os to reduced speed internal
logic.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORT8850L-2BMN680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT8850L-2BMN680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT8850L-3BM680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT8850L-3BMN680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT9303 | 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
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