參數(shù)資料
型號： ORT82G5-2BM680
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA680
封裝： PLASTIC, BGA-680
文件頁數(shù)： 96/110頁
文件大小： 1459K
代理商： ORT82G5-2BM680
86
Lattice Semiconductor
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Pin Information (continued)
Package Pinouts
Table 33 provides the package pin and pin function for the ORT82G5 FPSC and packages. The bond pad name is
identied in the PIO nomenclature used in the ORCA Foundry design editor. The Bank column provides information
as to which output voltage level bank the given pin is in. The Group column provides information as to the group of
pins the given pin is in. This is used to show which VREF pin is used to provide the reference voltage for single-
ended limited-swing I/Os. If none of these buffer types (such as SSTL, GTL, HSTL) are used in a given group, then
the VREF pin is available as an I/O pin.
When the number of FPGA bond pads exceeds the number of package pins, bond pads are unused. When the
number of package pins exceeds the number of bond pads, package pins are left unconnected (no connects).
When a package pin is to be left as a no connect for a specic die, it is indicated as a note in the device column for
the FPGA. The tables provide no information on unused pads.
As shown in the pair columns in Table 33, differential pairs and physical locations are numbered within each bank
(e.g., L19C-A0 is the nineteenth pair in an associated bank). A C indicates complementary differential, whereas a T
indicates true differential. An _A0 indicates the physical location of adjacent balls in either the horizontal or vertical
direction. Other physical indicators are as follows:
■
_A1 indicates one ball between pairs.
■
_A2 indicates two balls between pairs.
■
_D0 indicates balls are diagonally adjacent.
■
_D1 indicates balls are diagonally adjacent, separated by one physical ball.
VREF pins, shown in the Pin Description column in Table 33, are associated to the bank and group (e.g.,
VREF_TL_01 is the VREF for group one of the top left (TL) bank.
相關PDF資料
PDF描述
ORT82G5-3BM680 FPGA, 1296 CLBS, 380000 GATES, PBGA680
OS10040280G-012 FIBER OPTIC RECEIVER, 1290-1600nm, PANEL MOUNT, FC/APC CONNECTOR
OT-WBSC-Y-A-10-X-9-M-3-05-FA FIBER OPTIC SPLITTER/COUPLER, 1X2PORT, 10.0, PANEL MOUNT, FC/APC CONNECTOR
OT-WBSC-Y-A-50-13-9-F-1-05-FA FIBER OPTIC SPLITTER/COUPLER, 1X2PORT, 50.0, PANEL MOUNT, FC/APC CONNECTOR
OT-WBSC-Y-A-50-X-9-O-1-99-SA FIBER OPTIC SPLITTER/COUPLER, 1X2PORT, 50.0, PANEL MOUNT, SC/APC CONNECTOR
相關代理商/技術參數(shù)
參數(shù)描述
ORT82G5-2BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-2BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-2F680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-2F680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-2FN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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