參數(shù)資料
型號： ORT82G5-2BM680
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA680
封裝： PLASTIC, BGA-680
文件頁數(shù)： 53/110頁
文件大小： 1459K
代理商： ORT82G5-2BM680
Lattice Semiconductor
47
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Memory Map (continued)
Table 18. Memory Map (continued)
Addr
(Hex)
Reg
#
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Default
Value
SERDES A Common Transmit and Receive Channel Conguration Registers
30004
—
PRBS_AA
Transmit and
Receive PRBS
Enable Bit, Bank A,
Channel A. When
PRBS = 1, the
PRBS generator on
the transmitter and
the PRBS checker
on the receiver are
enabled. PRBS = 0
on device reset.
MASK_AA
Transmit and
Receive Alarm Mask
Bit, Bank A, Channel
A. When MASK = 1,
the transmit and
receive alarms of a
channel are pre-
vented from generat-
ing an interrupt. This
MASK bit overrides
the individual alarm
mask bits in the
Alarm Mask Regis-
ters. MASK = 1 on
device reset.
SWRST_AA
Transmit and Receive
Software Reset Bit,
Bank A, Channel A.
When SWRST = 1, this
bit provides the same
function as the hard-
ware reset, except all
conguration register
settings are preserved.
This is not a self-clear-
ing bit. Once set, this bit
must be cleared by writ-
ing a 0 to it. SWRST = 0
on device reset.
————
TESTEN_AA
Transmit and Receive Test
Enable Bit, Bank A, Channel
A. When TESTEN = 1, the
transmit and receive sections
are placed in test mode.
TESTEN = 0 on device reset.
When the global test enable
bit GTESTEN = 0, the indi-
vidual channel test enable
bits are used to selectively
place a channel in test or
normal mode. When GTES-
TEN = 1, all channels are set
to test mode regardless of
their TESTEN setting.
40
30014
—
PRBS_AB
Transmit and
Receive PRBS
Enable Bit, Bank A,
Channel B. When
PRBS = 1, the
PRBS generator on
the transmitter and
the PRBS checker
on the receiver are
enabled. PRBS = 0
on device reset.
MASK_AB
Transmit and
Receive Alarm Mask
Bit, Bank A, Channel
B. When MASK = 1,
the transmit and
receive alarms of a
channel are pre-
vented from generat-
ing an interrupt. This
MASK bit overrides
the individual alarm
mask bits in the
Alarm Mask Regis-
ters. MASK = 1 on
device reset.
SWRST_AB
Transmit and Receive
Software Reset Bit,
Bank A, Channel B.
When SWRST = 1, this
bit provides the same
function as the hard-
ware reset, except all
conguration register
settings are preserved.
This is not a self-clear-
ing bit. Once set, this bit
must be cleared by writ-
ing a 0 to it. SWRST = 0
on device reset.
————
TESTEN_AB
Transmit and Receive Test
Enable Bit, Bank A, Channel
B. When TESTEN = 1, the
transmit and receive sections
are placed in test mode.
TESTEN = 0 on device reset.
When the global test enable
bit GTESTEN = 0, the indi-
vidual channel test enable
bits are used to selectively
place a channel in test or
normal mode. When GTES-
TEN = 1, all channels are set
to test mode regardless of
their TESTEN setting.
40
30024
—
PRBS_AC
Transmit and
Receive PRBS
Enable Bit, Bank A,
Channel C. When
PRBS = 1, the
PRBS generator on
the transmitter and
the PRBS checker
on the receiver are
enabled. PRBS = 0
on device reset.
MASK_AC
Transmit and
Receive Alarm Mask
Bit, Bank A, Channel
C. When MASK = 1,
the transmit and
receive alarms of a
channel are pre-
vented from generat-
ing an interrupt. This
MASK bit overrides
the individual alarm
mask bits in the
Alarm Mask Regis-
ters. MASK = 1 on
device reset.
SWRST_AC
Transmit and Receive
Software Reset Bit,
Bank A, Channel C.
When SWRST = 1, this
bit provides the same
function as the hard-
ware reset, except all
conguration register
settings are preserved.
This is not a self-clear-
ing bit. Once set, this bit
must be cleared by writ-
ing a 0 to it. SWRST = 0
on device reset.
————
TESTEN_AC
Transmit and Receive Test
Enable Bit, Bank A, Channel
C. When TESTEN = 1, the
transmit and receive sections
are placed in test mode.
TESTEN = 0 on device reset.
When the global test enable
bit GTESTEN = 0, the indi-
vidual channel test enable
bits are used to selectively
place a channel in test or
normal mode. When GTES-
TEN = 1, all channels are set
to test mode regardless of
their TESTEN setting.
40
30034
—
PRBS_AD
Transmit and
Receive PRBS
Enable Bit, Bank A,
Channel D. When
PRBS = 1, the
PRBS generator on
the transmitter and
the PRBS checker
on the receiver are
enabled. PRBS = 0
on device reset.
MASK_AD
Transmit and
Receive Alarm Mask
Bit, Bank A, Channel
D. When MASK = 1,
the transmit and
receive alarms of a
channel are pre-
vented from generat-
ing an interrupt. This
MASK bit overrides
the individual alarm
mask bits in the
Alarm Mask Regis-
ters. MASK = 1 on
device reset.
SWRST_AD
Transmit and Receive
Software Reset Bit,
Bank A, Channel D.
When SWRST = 1, this
bit provides the same
function as the hard-
ware reset, except all
conguration register
settings are preserved.
This is not a self-clear-
ing bit. Once set, this bit
must be cleared by writ-
ing a 0 to it. SWRST = 0
on device reset.
————
TESTEN_AD
Transmit and Receive Test
Enable Bit, Bank A, Channel
D. When TESTEN = 1, the
transmit and receive sections
are placed in test mode.
TESTEN = 0 on device reset.
When the global test enable
bit GTESTEN = 0, the indi-
vidual channel test enable
bits are used to selectively
place a channel in test or
normal mode. When GTES-
TEN = 1, all channels are set
to test mode regardless of
their TESTEN setting.
40
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ORT82G5-2BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-2BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-2F680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-2F680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-2FN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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