參數(shù)資料
型號(hào)： ORT82G5-2BM680
廠(chǎng)商： LATTICE SEMICONDUCTOR CORP
元件分類(lèi)： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA680
封裝： PLASTIC, BGA-680
文件頁(yè)數(shù)： 36/110頁(yè)
文件大?。?/td> 1459K
代理商： ORT82G5-2BM680
Lattice Semiconductor
31
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Backplane Transceiver Core Detailed
Description (continued)
The de-multiplexed, receive word outputs to the FPGA
are shown in Figure 14. These are each 40 bits wide.
There are eight of these interfaces, one for each data
lane. Each consist of four 10-bit characters, or four
decoded characters (each 8 bits + 1 bit K_CTRL) +
CH248_SYNCx status indicator bit depending on set-
ting of NOCHALGNx control register bits. The NOCH-
ALGNx register bit decides whether data into the FPGA
(MRWDxy] comes from the channel alignment FIFOs
or deMUX block. Note that there is one control bit for a
bank of channels, for a total of two control bits. Also,
note that while 10 bits are provided for each character
when NOCHALGNx = 1, only the lower 9 bits of each
character will be meaningful if the 8B10BR bit is cong-
ured to 1 for that SERDES channel.
With x representing the bank (placeholder for A or B)
and y representing the channel (placeholder for A, B,
C, or D) the 40-bit MRWDxy[39:0] is allocated as in
In the receive path, each channel is provided with a 24
word x 36-bit FIFO. The FIFO can perform two tasks:
(1) to change the clock domain from receive clock to a
clock from the FPGA side, and (2) to align the receive
data over 2, 4, or 8 channels. This FIFO allows a timing
budget of +/- 230.4 ns that can be allocated to skew
between the data lanes and for transfer to the system
clock. The input to the FIFO consists of 36-bit demulti-
plexed data, RWBYTESYNC[3:0], RWDx[31:0], and
RWBIT8x[3:0].
The four RWBYTESYNC bits are control signals, e.g.,
they can be the COMMADET signals indicating the
presence of COMMA character. The other 32 RWD bits
are the 4 characters from the 8b/10b decoder. The
RWBIT8 indicates the presence of Km.n control char-
acter in the receive data byte. Only RWBIT8 and RWD
inputs are stored in the FIFO. During alignment pro-
cess, RWBYTESYNC[3] is used to synchronize multi-
ple channels. If a channel is not in any alignment
group, it will set the FIFO-write-address to the begin-
ning of the FIFO, and will set the FIFO-read-address to
the middle of the FIFO, at the rst assertion of
RWBYTESYNC[3] after reset or after the resync com-
mand.
The RX_FIFO_MIN register bits can be used to control
the threshold for minimum unused buffer space in the
alignment FIFOs between read and write pointers
before OVFL status is agged. The synchronization
algorithm consists of a down counter which starts to
count down by 1 from its initial value of 18 (decimal)
when an alignment character from any channel within
an alignment group has been received. When align-
ment characters from all channels within the alignment
group have been received and count < RX_FIFO_MIN,
an OVFL status is agged. Once the alignment charac-
ters within the alignment group have been received,
the count is decremented by 2 until 0 is reached. Data
is then read from the FIFOs and output to the FPGA.
For every alignment group, there is an OVFL and OOS
status register bit. The OOS bit is agged when the
down counter in the synchronization algorithm has
reached a value of 0 and alignment characters from all
channels within an alignment group have not been
received. In the memory map section OOS is referred
to as SYNC[2,4]_[A1,A2,B1,B2]_OOS, SYNC8_OOS.
OVFL is referred to as
SYNC[2,4]_[A1,A2,B1,B2]_OVFL, SYNC8_OVFL.
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