參數(shù)資料
型號(hào)： ORT82G5-2BM680
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA680
封裝： PLASTIC, BGA-680
文件頁(yè)數(shù)： 52/110頁(yè)
文件大?。?/td> 1459K
代理商： ORT82G5-2BM680
46
Lattice Semiconductor
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Memory Map (continued)
Table 18. Memory Map (continued)
Addr
(Hex)
Reg
#
DB0
DB1
DB2
DB3
DB4
DB5 DB6 DB7
Default
Value
SERDES A Receive Channel Conguration Registers
30003
—
RXHR_AA
Receive Half Rate
Selection Bit, Bank
A, Channel A.
When RXHR = 1,
the RBC[1:0] clocks
are issued at half
the scheduled rate
of the reference
clock. RXHR = 0 on
device reset.
PWRDNR_AA
Receiver Power
Down Control Bit,
Bank A, Channel A.
When PWRDNR =
1, sections of the
receive hardware
are powered down
to conserve power.
PWRDNR = 0 on
device reset.
SDOVRIDE_AA
Receive Signal Detect
Alarm Override Bit,
Bank A, Channel A.
When SDOVRIDE = 1,
the energy detector
output from the
receiver is masked.
Thus, when there is no
receive data, the pow-
erdown function is dis-
abled and the
corresponding SDON
alarm is suppressed.
SDOVRIDE = 1 on
device reset.
8B10BR_AA
Receive 8B/10B
Decoder Enable Bit,
Bank A, Channel A.
When 8B10BR = 1,
the 8B/10B decoder
on the receive path
is enabled. Other-
wise, it is bypassed.
8B10BR = on device
reset.
LINKSM_AA
Link State Machine
Enable Bit, Bank A,
Channel A. When
LINKSM = 1, the
receiver link state
machine is enabled.
Otherwise, the link
state machine is dis-
ables. LINKSM = 0
on device reset.
———
20
30013
—
RXHR_AB
Receive Half Rate
Selection Bit, Bank
A, Channel B.
When RXHR = 1,
the RBC[1:0] clocks
are issued at half
the scheduled rate
of the reference
clock. RXHR = 0 on
device reset.
PWRDNR_AB
Receiver Power
Down Control Bit,
Bank A, Channel B.
When PWRDNR =
1, sections of the
receive hardware
are powered down
to conserve power.
PWRDNR = 0 on
device reset.
SDOVRIDE_AB
Receive Signal Detect
Alarm Override Bit,
Bank A, Channel B.
When SDOVRIDE = 1,
the energy detector
output from the
receiver is masked.
Thus, when there is no
receive data, the pow-
erdown function is dis-
abled and the
corresponding SDON
alarm is suppressed.
SDOVRIDE = 1 on
device reset.
8B10BR_AB
Receive 8B/10B
Decoder Enable Bit,
Bank A, Channel B.
When 8B10BR = 1,
the 8B/10B decoder
on the receive path
is enabled. Other-
wise, it is bypassed.
8B10BR = on device
reset.
LINKSM_AB
Link State Machine
Enable Bit, Bank A,
Channel B. When
LINKSM = 1, the
receiver link state
machine is enabled.
Otherwise, the link
state machine is dis-
ables. LINKSM = 0
on device reset.
———
20
30023
—
RXHR_AC
Receive Half Rate
Selection Bit, Bank
A, Channel C.
When RXHR = 1,
the RBC[1:0] clocks
are issued at half
the scheduled rate
of the reference
clock. RXHR = 0 on
device reset.
PWRDNR_AC
Receiver Power
Down Control Bit,
Bank A, Channel C.
When PWRDNR =
1, sections of the
receive hardware
are powered down
to conserve power.
PWRDNR = 0 on
device reset.
SDOVRIDE_AC
Receive Signal Detect
Alarm Override Bit,
Bank A, Channel C.
When SDOVRIDE = 1,
the energy detector
output from the
receiver is masked.
Thus, when there is no
receive data, the pow-
erdown function is dis-
abled and the
corresponding SDON
alarm is suppressed.
SDOVRIDE = 1 on
device reset.
8B10BR_AC
Receive 8B/10B
Decoder Enable Bit,
Bank A, Channel C.
When 8B10BR = 1,
the 8B/10B decoder
on the receive path
is enabled. Other-
wise, it is bypassed.
8B10BR = on device
reset.
LINKSM_AC
Link State Machine
Enable Bit, Bank A,
Channel C. When
LINKSM = 1, the
receiver link state
machine is enabled.
Otherwise, the link
state machine is dis-
ables. LINKSM = 0
on device reset.
———
20
30033
—
RXHR_AD
Receive Half Rate
Selection Bit, Bank
A, Channel D.
When RXHR = 1,
the RBC[1:0] clocks
are issued at half
the scheduled rate
of the reference
clock. RXHR = 0 on
device reset.
PWRDNR_AD
Receiver Power
Down Control Bit,
Bank A, Channel D.
When PWRDNR =
1, sections of the
receive hardware
are powered down
to conserve power.
PWRDNR = 0 on
device reset.
SDOVRIDE_AD
Receive Signal Detect
Alarm Override Bit,
Bank A, Channel D.
When SDOVRIDE = 1,
the energy detector
output from the
receiver is masked.
Thus, when there is no
receive data, the pow-
erdown function is dis-
abled and the
corresponding SDON
alarm is suppressed.
SDOVRIDE = 1 on
device reset.
8B10BR_AD
Receive 8B/10B
Decoder Enable Bit,
Bank A, Channel D.
When 8B10BR = 1,
the 8B/10B decoder
on the receive path
is enabled. Other-
wise, it is bypassed.
8B10BR = on device
reset.
LINKSM_AD
Link State Machine
Enable Bit, Bank A,
Channel D. When
LINKSM = 1, the
receiver link state
machine is enabled.
Otherwise, the link
state machine is dis-
ables. LINKSM = 0
on device reset.
———
20
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