參數(shù)資料
型號： ORLI10G-3BM416
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA416
封裝： PLASTIC, BGA-416
文件頁數(shù)： 28/76頁
文件大?。?/td> 1222K
代理商： ORLI10G-3BM416
34
Lattice Semiconductor
Data Sheet
January 15, 2002
and ORLI12G Gbits/s Line Interface FPSC
ORCA ORLI10G Quad 2.5 Gbits/s, 10 Gbits/s
XGMII ORCA 4E Receive Analysis
XGMII Considerations
The stringent 10 Gbit media independent interface (XGMII) specications from the IEEE 802.3ae standards are
met in the FPGA side of the ORLI10G device. This interface is implemented in the PCS IP core and targeted to the
ORLI10G FPSC. Figure 17 and Table 4 show a simplied block diagram for this interface and the receive voltage
levels for the HSTL inputs to the ORLI10G device. Other I/O standards are also possible, such as SSTL or HSTL,
with a reference voltage of 1.8 V. Further details are available in the Series 4 I/O application note and the Series 4
Fast Input DDR and Output DDR with Clock Forwarding Application Note.
The ORLI10G device meets the 480 ps input setup time and 480 ps input hold time requirements for the XGMII
receiver inputs into the FPGA side of the FPSC with the embedded I/O DDR cells on the FPGA side of the FPSC.
The PLLs are not used on input because this is a forward clocked interface. The ORLI10G meets the clock-to-out
specication on the XGMII DDR outputs by using the output shift register to produce a nonduty, cycle-dependent
output. An embedded output DDR capability is also available. The output clock is then centered around this data
eye using internal PLLs.
There are two considerations to note about the pinout location of the XGMII input clocks:
1. The XGMII input clocks must be located at the C pad of the programmable I/O cells (PICs). In the pinout
tables, the pads are labeled on a pin-by-pin basis. For example, a pin whose pad is referenced as PL1C can
be used as an XGMII input clock, but pins referenced as PL1A, PL1B, or PL1D cannot be used as an XGMII
input clock.
2. The XGMII input data pins can be no further then six PICs away from the XGMII input clock pin. This means
that in the 416 PBGA package, the clock needs to be driven on two pins to be able to clock in the 32-bit XGMII
input data bus.
Due to the strict pinout locations mentioned above, when implementing a XGMII interface, the microprocessor
interface (MPI) will not be available in the 416 PBGA package, though this is typically not an issue due to an SMI
interface included with the ORLI10G PCS IP core.
1550.a(F)
Figure 17. Simplied XGMII Block Diagram
HSTL
CLOCK
VDDIO
VDD15
VDDIO = 1.5 V NOM
HSTL
VDDIO = 1.5 V NOM
VREF
VDDIO ÷ 2
DDR DATA
CUSTOMER DEVICE
ORLI10G
SYSTEM
INTERFACE
LINE
INTERFACE
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