參數(shù)資料
型號： ORLI10G-3BM416
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA416
封裝： PLASTIC, BGA-416
文件頁數(shù)： 25/76頁
文件大?。?/td> 1222K
代理商： ORLI10G-3BM416
Lattice Semiconductor
31
Data Sheet
January 15, 2002
and ORLI12G Gbits/s Line Interface FPSC
ORCA ORLI10G Quad 2.5 Gbits/s, 10 Gbits/s
ORLI10G Embedded PLLs
The ORLI10G embedded (transmit and receive) PLLs are based on the 4E series FPGA high-speed programma-
ble PLL (HPPLL). The 4E PLL consists of a phase/frequency detector (PFD), a charge pump/lter, a multitap volt-
age controlled oscillator (VCO), a duty cycle synthesis circuitry, a power regulator, two programmable dividers,
phase shift selector multiplexers, a lock signal generator, and a current DAC. A block diagram of the programmable
PLL is shown in Figure 15. The receive path RX1_PLL and transmit path TX1_PLL, which can be programmed to
create a N/M frequency clock, are based on this design.
The receive path RX2_PLL and transmit path TX2_PLL create a X1 clock. This is essentially the same PLL without
the M and N divider.
The RCKI input to the PLLs comes from an input clock to the ORLI10G that has been divided in frequency by
either 4 or 8 (programmable). As shown in Figure 3, RX1_PLL and RX2_PLL are driven by the divided version of
RX_CLK_IN0. As shown in Figure 4, TX1_PLL and TX2_PLL are driven by the divided versions of TX_CLK_IN. It
should be noted that the speed of the ORLI10G line interface is therefore either 4x or 8x the operating speed of the
embedded PLLs.
The clock feedback loops for the RX2_PLL and TX2_PLL should be routed from the clock network in the FPGA
core to compensate for the routing delays to the FPGA logic interface. The source to the TX2_FBCKI or
RX2_FBCKI inputs must come from an FPGA clock network driven by the VCO output (otherwise, any phase shift-
ing on VCOP is removed by the feedback loops). In this way, the clock skew at the embedded core/FPGA logic
boundary is zero for the receive and transmit PLLs.
All PLLs include a phase shift selector which allows phase shift adjustments of each clock in increments of 1/8 the
period of the clock. This phase shifted output is available on the VCOP output of the PLL. All functions of the
embedded core PLLs are user controlled through a GUI provided with the ORLI10G design kit software.
1331(F)
Figure 15. ORLI10G Programmable PLL Block Diagram
RCKI
M<5:0>
N<5:0>
SEL<2:0>
BYPASS
M
DIVIDER
N
DIVIDER
PFD
LOCK
GENERATOR
CHARGE PUMP
AND FILTER
VCO
PHASE
SELECT
RCKO
LOCK
VCOP
VCO
TX2_FBCKI
RX2_FBCKI
相關(guān)PDF資料
PDF描述
ORLI10G-3BM680 FPGA, 1296 CLBS, 380000 GATES, PBGA680
ORLI10G1BM680-DB FPGA, 1296 CLBS, 333000 GATES, PBGA680
ORLI10G2BM680-DB FPGA, 1296 CLBS, 333000 GATES, PBGA680
ORLI10G3BM680-DB FPGA, 1296 CLBS, 333000 GATES, PBGA680
ORT82G5-1BM680 FPGA, 1296 CLBS, 380000 GATES, PBGA680
相關(guān)代理商/技術(shù)參數(shù)
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ORLI10G-3BMN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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