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參數(shù)資料
| 型號： | ORLI10G-2BM680 |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| 封裝： | PLASTIC, BGA-680 |
| 文件頁數(shù)： | 7/76頁 |
| 文件大?。?/td> | 1222K |
| 代理商： | ORLI10G-2BM680 |
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Lattice Semiconductor
15
Data Sheet
January 15, 2002
and ORLI12G Gbits/s Line Interface FPSC
ORCA ORLI10G Quad 2.5 Gbits/s, 10 Gbits/s
Receive Path Details
In the receive path, the ORLI10G embedded core can
be broken down into three sections: the high-speed line
interface, the demultiplexer, and the receive-side
onboard PLLs. Note that both transmit and receive
PLLs are in addition to the four programmable PLLs
(PPLLs) in the FPGA portion of the ORLI10G.
Line Interface
In the receive path, 16-bit data and associated clocks
are inputs to the line interface. Typical data rates are
expected to range from 622 Mbits/s to 850 Mbits/s for
most applications. The 16-bit LVDS input data bus is
actually composed of four 4-bit data buses with one
clock for each 4-bit data bus. In the 10G mode, all four
input clocks are tied together internal to the device and
driven by the lowest-order input clock. In 2.5G mode,
the four clocks may be asynchronous to each other.
The ORLI10G uses LVDS (low-voltage differential sig-
naling) drivers/receivers, which are intended to provide
point-to-point connection between the ORLI10G and
optical transceiver (MUX/deMUX) parts. The LVDS
inputs are hot-swap compatible and can connect to
other vendor's LVDS I/O buffers. The LVDS inputs are
terminated with a 100 resistor to improve perfor-
mance.
The receive line interface on the ORLI10G can connect
to devices that are compliant to either the XSBI stan-
dard or the SFI-4 standard. The major difference for
these standards is that for XSBI (IEEE 802.3ae version
2.1), the least signicant bit [0] is received rst after
deserialization by the external deMUX device, whereas
SFI-4 receives the most signicant bit rst. In some
cases, bits [15:0] on the ORLI10G should be con-
nected to bits [0:15] on the device to which the
ORLI10G device interfaces. An example of this is the
PCS IP core in the ORLI10G when the ORLI10G is
connected to an XSBI version 2.1 device.
It should be noted that IEEE 802.3ae version 3.1 to
D3.4 (version D3.4 is the latest draft version of this
specication as of the writing of this data sheet) swaps
XSBI so that the most signicant bit is received rst,
thus requiring that bits [0:15] on the ORLI10G be con-
nected directly to bits [0:15] on the XSBI device.
DeMUX
The demultiplexer takes the high-speed line data and
clocks and converts the data and clock to rates appro-
priate for transfer to the FPGA logic. The demultiplexer
supports two modes of operation:
■
Divide-by-8 10G (or single channel):
The demultiplexer converts the incoming 16 bits of data
at 622 Mbits/s to 850 Mbits/s into 128 bits at 78 Mbits/s
to 106 Mbits/s. The incoming clocks are divided by 8.
2.5G (or quad channel): The demultiplexer converts the
incoming four bits of data at 622 Mbits/s to 850 Mbits/s
into 32 bits at 78 Mbits/s to 106 Mbits/s. The associated
clock is also divided by 8. This is repeated four times
with each 4-bit data/clock group assumed to be asyn-
chronous to the others.
■
Divide-by-4:
10G (or single channel): The demultiplexer converts the
incoming 16 bits of data at 622 Mbits/s to
850 Mbits/s into 64 bits at 156 Mbits/s to 212 Mbits/s.
The incoming clocks are divided by 4.
2.5G (or quad channel): The demultiplexer converts the
incoming 4 bits of data at 622 Mbits/s to 850 Mbits/s
into 16 bits at 156 Mbits/s to 212 Mbits/s. The associ-
ated clock is also divided by 4. This is repeated four
times with each 4-bit data/clock group assumed to be
asynchronous to the others.
Onboard Receive PLLs
The function of the onboard PLLs is to align the system
data with the line data, which will be at a slightly higher
rate owing to the addition of the overhead bits. There
are two PLLs on the receive path. The input to the rst
PLL, RX1_PLL (see Figure 3), is the divided down low-
est-order clock from the demultiplexer. The RX1_PLL
generates a clock with a user-dened frequency ratio of
M/N to the divided clock. This clock would generally be
used to compensate for different data rates due to
overhead bits. M and N can independently be set from
1 to 8.
The RX2_PLL also takes its input from the divided
down clock and is used to provide a balanced divided
clock across the FPGA-embedded core interface.
The RX2_PLL has a feedback path that compensates
for routing delays to the embedded core/FPGA logic
interface for minimum clock skew.
In addition, the user can specify an additional skew on
each clock in increments of 1/8 the clock period.
The selection of the deMUX width (and corresponding
clock division value), the RX1_PLL M and N values,
and the additional skew for RX1_PLL and RX2_PLL
are specied by the user in a GUI interface provided in
the ORLI10G design kit.
A detailed block diagram of the receive path in shown
in Figure 3.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ORLI10G-3BM416 | FPGA, 1296 CLBS, 380000 GATES, PBGA416 |
| ORLI10G-3BM680 | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| ORLI10G1BM680-DB | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| ORLI10G2BM680-DB | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| ORLI10G3BM680-DB | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORLI10G-2BM680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G-2BM680I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G-2BMN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G-2BMN680I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G-3BM680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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