參數(shù)資料
型號： ORLI10G-2BM680
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA680
封裝： PLASTIC, BGA-680
文件頁數(shù)： 18/76頁
文件大?。?/td> 1222K
代理商： ORLI10G-2BM680
Lattice Semiconductor
25
Data Sheet
January 15, 2002
and ORLI12G Gbits/s Line Interface FPSC
ORCA ORLI10G Quad 2.5 Gbits/s, 10 Gbits/s
ORLI10G Multiplexer (Tx) Detail
The multiplexer module converts the incoming 128 bits
of data from the FPGA logic at 78 MHz/106 MHz or
64 bits of data from the FPGA logic at 156 MHz/
212 MHz into 16 bits of data at 622 MHz/850 MHz. It
has been implemented as two stages. The rst stage
deinterleaves each incoming byte into a different byte
stream that can be serially output on the output data
pins. The second stage outputs these bytes into 16 bits
or four groups of 4 bits, depending upon the mode of
operation. Functionally, the multiplexer architecture
consists of three blocks: the parallel-to-serial conver-
sion, the counters, and the deinterleaving.
Two options are available for the transmit clocks in both
2.5G and 10G modes. The clock signals
TX_CLK_IN[3:0] can be used to transfer data to the
internal core or an internal clock can be used. The pre-
ferred method is to use the internal clock. Two options
are also available for the enable signals in 2.5G and
10G modes. The enable signals TX_ENB8_IN[3:0] can
be used or they can be generated internally. The pre-
ferred method is to use the internal enables.
For 2.5G or 10G divide-by-8 mode, the rst stage of the
line interface module deinterleaves each incoming byte
of data into a different byte stream on the 78 MHz/
106 MHz (TX_CLK8_IN[3:0] or internal) clock. This
data is then registered on the rising edge of the
622 MHz/850 MHz (TX_CLK_IN) clock at the falling
edge of the 78 MHz/106 MHz clock. The enable inputs
(TX_ENB8_IN[3:0] or internal) are used to transfer data
from the low-speed clock to the high-speed clock, as
well as synchronizing the counters of parallel-to-serial
conversion which are running at the high-speed clock.
Generally, these enables are generated in the embed-
ded core and the TX_ENB8_IN[3:0] signals to the
embedded core are not used.
For 2.5G or 10G divide-by-4 mode, the rst stage of the
line interface module deinterleaves each incoming byte
of data into a different byte stream on the 156 MHz/
212 MHz (TX_CLK8_IN[3:0] or internal) clock. This
data is then registered on the rising edge of the
622 MHz/850 MHz (TX_CLK_IN) clock at the falling
edge of the 156 MHz/212 MHz clock. The enable inputs
(TX_ENB8_IN[3:0] or internal) are used to transfer data
from the low-speed clock to the high-speed clock, as
well as synchronizing the counters of parallel-to-serial
conversion which are running at the high-speed clock.
Again, both TX_CLK8_IN[3:0] and TX_ENB8_IN[3:0]
are not generally used.
In 2.5G or 10G modes, the enable inputs
(TX_ENB8_IN[3:0]) are required to be four (divide by 4)
or eight (divide by 8) TX_CLK_IN clock cycles wide. If
they are used, they have to be synchronous to their
corresponding TX_CLK8_IN[3:0] clock. Each of these
four TX_CLK8_IN[3:0] clocks must also be frequency
locked to the TX_CLK_IN signal.
In both 2.5G and 10G modes, the TX_CLK_OUT[3:0]
clock outputs from the ORLI10G are provided for trans-
ferring each 4 bits of data per clock.
For both 2.5G modes and 10G modes, all data to be
transmitted to the embedded core must be frequency
locked to the TX_CLK_IN signal. Thus, the divided ver-
sion of this clock found at the embedded core interface
should always be used to transfer data from the FPGA
logic to the embedded core. These clock signals are
available from the TX PLL outputs (TX1_VCO,
TX1_VCOP, TX2_VCO, TX2_VCOP). Figure 10 shows
the valid data input bits to the multiplexer in each of the
four modes (divide-by-8, 10G and 2.5G modes, and
divide-by-4, 10G and 2.5G modes). Figure 11—
Figure 14 show the multiplexer input transmit reference
clock, data, enable, and clock waveforms and output
clock and data waveforms for all four modes.
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ORLI10G-2BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-2BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-2BMN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-2BMN680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-3BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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