參數(shù)資料
型號(hào)： ORLI10G-2BM416
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA416
封裝： PLASTIC, BGA-416
文件頁(yè)數(shù)： 45/76頁(yè)
文件大?。?/td> 1222K
代理商： ORLI10G-2BM416
Lattice Semiconductor
5
Data Sheet
January 15, 2002
and ORLI12G Gbits/s Line Interface FPSC
ORCA ORLI10G Quad 2.5 Gbits/s, 10 Gbits/s
Programmable Features (continued)
■
Enhanced twin-quad programmable function unit
(PFU):
— Eight 16-bit look-up tables (LUTs) per PFU.
— Nine user registers per PFU, one following each
LUT, organized to allow two nibbles to act inde-
pendently, plus one extra for arithmetic operations.
— New register control in each PFU has two inde-
pendent programmable clocks, clock enables,
local set/reset, and data selects.
— New LUT structure allows exible combinations of
LUT4, LUT5, new LUT6, 4 ' 1 MUX, new 8 ' 1
MUX, and ripple mode arithmetic functions in the
same PFU.
— 32 x 4 RAM per PFU, congurable as single- or
dual-port. Create large, fast RAM/ROM blocks
(128 x 8 in only eight PFUs) using the SLIC
decoders as bank drivers.
— Soft-wired LUTs (SWL) allow fast cascading of up
to three levels of LUT logic in a single PFU
through fast internal routing, which reduces rout-
ing congestion and improves speed.
— Flexible fast access to PFU inputs from routing.
— Fast-carry logic and routing to all four adjacent
PFUs for nibble-wide, byte-wide, or longer arith-
metic functions, with the option to register the PFU
carry-out.
■
Abundant high-speed buffered and nonbuffered rout-
ing resources provide 2x average speed improve-
ments over previous architectures.
■
Hierarchical routing optimized for both local and glo-
bal routing with dedicated routing resources. This
results in faster routing times with predictable and
efcient performance.
■
SLIC provides eight 3-stable buffers, up to a 10-bit
decoder, and PAL-like and-or-invert (AOI) in each
programmable logic cell.
■
New 200 MHz embedded quad-port RAM blocks, two
read ports, two write ports, and two sets of byte lane
enables. Each embedded RAM block can be cong-
ured as:
— 1—512 x 18 (quad-port, two read/two write) with
optional built-in arbitration.
— 1—256 x 36 (dual-port, one read/one write).
— 1—1k x 9 (dual-port, one read/one write).
— 2—512 x 9 (dual-port, one read/one write for
each).
— 2 RAMs with arbitrary number of words whose
sum is 512 or less by 18 (dual-port, one read/one
write).
— Supports joining of RAM blocks.
— Two 16 x 8-bit content addressable memory
(CAM) support.
— FIFO 512 x 18, 256 x 36, 1k x 9, or dual 512 x 9.
— Constant multiply (8 x 16 or 16 x 8).
— Dual variable multiply (8 x 8).
■
Embedded 32-bit internal system bus plus 4-bit par-
ity interconnects FPGA logic, microprocessor inter-
face (MPI), embedded RAM blocks, and embedded
standard cell blocks with 100 MHz bus performance.
Included are built-in system registers that act as the
control and status center for the device.
■
Built-in testability:
— Full boundary scan (IEEE 1149.1 and draft 1149.2
JTAG) for the programmable I/Os only.
— Programming and readback through boundary-
scan port compliant to IEEE Draft 1532:D1.7.
— TS_ALL testability function to 3-state all I/O pins.
— New temperature-sensing diode.
■
Improved built-in clock management with program-
mable phase-locked loops (PPLLs) provides opti-
mum clock modication and conditioning for phase,
frequency, and duty cycle from 20 MHz up to
420 MHz. Multiplication of input frequency up to 64x
and division of input frequency down to 1/64x is pos-
sible.
■
New cycle stealing capability allows a typical 15% to
40% internal speed improvement after nal place
and route. This feature also enables compliance with
many setup/hold and clock-to-out I/O specications,
and may provide reduced ground bounce for output
buses by allowing exible delays of switching output
buffers.
相關(guān)PDF資料
PDF描述
ORLI10G-2BM680 FPGA, 1296 CLBS, 380000 GATES, PBGA680
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ORLI10G-3BM680 FPGA, 1296 CLBS, 380000 GATES, PBGA680
ORLI10G1BM680-DB FPGA, 1296 CLBS, 333000 GATES, PBGA680
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