參數(shù)資料
型號： ORLI10G-2BM416
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA416
封裝： PLASTIC, BGA-416
文件頁數(shù)： 32/76頁
文件大小： 1222K
代理商： ORLI10G-2BM416
38
Lattice Semiconductor
Data Sheet
January 15, 2002
and ORLI12G Gbits/s Line Interface FPSC
ORCA ORLI10G Quad 2.5 Gbits/s, 10 Gbits/s
Timing Characteristics
Receive Input Data Interface
Receive STS-48/STS-192 (2.5G/10G) Data Inputs
Figure 18 illustrates the timing for the receive STS-48/STS-192 data stream. Both the clock and data pins are low-
voltage differential signal (LVDS) input buffers. The expected clock rate is 622 MHz—850 MHz, and the receive
data is clocked on the rising edge of the clock. In 2.5G mode, each of the four channels uses one set of one
RX_CLK_INn and four RX_DAT_INn data pins. In 10G mode, only RX_CLK_IN0 is used, along with the
RX_DAT_IN[15:0] pins. The timing values for the diagram in Figure 18 are given in Table 13.
5-9085.b (F)
Figure 18. Receive Input Data Timing
Table 13. Receive Data Input Timing
It is recommended that the Rx clock be inverted by crossing the LVDS pin pair, that is, connect the
RX_CLK_IN_P[3:0] input signal on the ORLI10G to the N (i.e., complement) clock output from the transmitting
device and connect the RX_CLK_IN_N[3:0] input on the ORLI10G to the P (i.e., true) clock output from the trans-
mitting device. This is because the embedded line interface on the ORLI10G requires the Rx data to be centered
on the Rx clock, and typically the devices that drive the ORLI10G transmit clock and data on the same clock edge.
Parameter
Symbol
–1
–2
–3
Unit
Min
Max
Min
Max
Min
Max
Clock Frequency
t1
—
667
—
790
—
850
MHz
Data Setup Time Required
t2
300
—
225
—
210
—
ps
Data Hold Time Required
t3
300
—
225
—
210
—
ps
RX_CLK_IN_P[3:0]
RX_DAT_IN_N[15:0]
t1
t3
t2
RX_CLK_IN_N[3:0]
RX_DAT_IN_P[15:0]
相關(guān)PDF資料
PDF描述
ORLI10G-2BM680 FPGA, 1296 CLBS, 380000 GATES, PBGA680
ORLI10G-3BM416 FPGA, 1296 CLBS, 380000 GATES, PBGA416
ORLI10G-3BM680 FPGA, 1296 CLBS, 380000 GATES, PBGA680
ORLI10G1BM680-DB FPGA, 1296 CLBS, 333000 GATES, PBGA680
ORLI10G2BM680-DB FPGA, 1296 CLBS, 333000 GATES, PBGA680
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORLI10G-2BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-2BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-2BMN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-2BMN680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-3BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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