參數(shù)資料
型號(hào): ORLI10G-2BM416
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: FPGA
英文描述: FPGA, 1296 CLBS, 380000 GATES, PBGA416
封裝: PLASTIC, BGA-416
文件頁數(shù): 27/76頁
文件大小: 1222K
代理商: ORLI10G-2BM416
Lattice Semiconductor
33
Data Sheet
January 15, 2002
and ORLI12G Gbits/s Line Interface FPSC
ORCA ORLI10G Quad 2.5 Gbits/s, 10 Gbits/s
Line Interface Circuit Specications
Power Supply Decoupling LC Circuit
The 622 MHz—850 MHz line interface macro contains both analog and digital circuitry. The line interface function,
for example, is implemented as primarily a digital function, but it relies on a conventional analog phase-locked loop
to provide its divided clocks. The internal analog phase-locked loop contains a voltage-controlled oscillator. This
circuit will be sensitive to digital noise generated from the rapid switching transients associated with internal logic
gates and parasitic inductive elements. Generated noise that contains frequency components beyond the band-
width of the internal phase-locked loop (about 3 MHz) will not be attenuated by the phase-locked loop and will
impact bit error rate directly. Thus, separate power supply pins are provided for these critical analog circuit ele-
ments.
Additional power supply ltering in the form of an LC pi lter section will be used between the power supply source
and these device pins as shown in Figure 16. The corner frequency of the LC lter is chosen based on the power
supply switching frequency, which is between 100 kHz and 300 kHz in most applications.
Capacitors C1 and C2 are large electrolytic capacitors to provide the basic cut-off frequency of the LC lter. For
example, the cut-off frequency of the combination of these elements might fall between 5 kHz and 50 kHz. Capac-
itor C3 is a smaller ceramic capacitor designed to provide a low-impedance path for a wide range of high-fre-
quency signals at the analog power supply pins of the device. The physical location of capacitor C3 must be as
close to the device lead as possible. Multiple instances of capacitors C3 can be used if necessary. The recom-
mended lter for the HSI macro is shown below: L = 4.7 H, RL = 1 , C1 = 0.01 F, C2 = 0.01 F, C3 = 4.7 F.
5-9344(F).a
Figure 16. Sample Power Supply Filter Network for Analog LI Power Supply Pins
C2
+
C3
+
TO DEVICE
VDDA_[7:4]
VSSA_[7:4]
C1
+
FROM POWER
SUPPLY SOURCE
L
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