參數(shù)資料
型號： OR3TP12-6PS240
英文描述： Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R
中文描述： 用戶可編程ASIC的特殊功能
文件頁數(shù)： 85/128頁
文件大?。?/td> 2450K
代理商： OR3TP12-6PS240
Lucent Technologies Inc.
85
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Target Controller Detailed Description
(continued)
Table 25. Configuration Space Assignment
(continued)
1. These values are intended to be custom assigned, per the intended application, by assigning constants via the FPGA configuration manager.
2. These bits exhibit special behavior per the PCI Specification:
— Reads behave normally.
— Writing a one clears the bit to 0.
— Writing a 0 has no effect on the bit.
3. Bytes 10—27 hex contain the base address registers (BARs).
— Any legal combination of memory and I/O BARs is permitted, as long as 64-bit BARs are naturally aligned, that is, they occupy bytes
10—17, 18—1F, or 20—27 hex.
— Memory BARs may be marked as prefetchable/nonprefetchable by setting/resetting bit 3; however, the PCI bus core’s behavior is not
affected by this setting. In particular, the Target read operation may discard unused FIFO read-ahead data even though the data space is
marked as nonprefetchable (this is not a violation since the nonprefetchable bit only says that data can’t be discarded once it has been
sent over the PCI bus; nevertheless, caution must be exercised when this bit is reset).
4. These signals are tied to the FPGA signal of the same name and are not initialized.
5. These bits exhibit special behavior per the CompactPCI Hot Swap Specification:
— Reads behave normally.
— Writing a one clears the bit to 0.
— Writing a 0 has no effect on the bit.
6. This 32-bit register is used during manufacturing test. Writes are not allowed; reads are allowed and cause no side effects, but the value
returned is undefined.
Bytes
40—41
Width
16
Bit
Description
Read/Write
Initial Value
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
FPGA Config. Command-Status Register:
Gsr
PCI Core Global Set/Reset
ConfigFPGA
Enable FPGA Config.
RdCfgN
Enable Readback
PrgmN
Reset FPGA Config. Logic
FastSlowN
Fast/Slow Config. Clock
BitErr_1
Error Signal from FPGA
BitErr_0
Error Signal from FPGA
—
Reserved
—
Reserved
Reserved
SRFull
Shift Reg. Full
SREmpty
Shift Reg. Empty
HandShakeErrorShift Reg. Error
InitN
FPGA’s INITN
Done
FPGA’s DONE
ASBMODE
Ready to Config
(Reserved)
FPGA Config. Data Register
Scratch Register
Reserved for Manufacturing Testing
Capability ID
Next Item
Hot Swap Control Status Register:
INS
Freshly
Inserted
EXT
Pending Extraction
Reserved
Reserved
LOO
LED ON/OFF
Reserved
EIM
enumn
Signal Mask
Reserved
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read/Only
Read Only
Read Only
Read Only
Read Only
Read/Write
Read/Write
Note 6
Read Only
Read Only
0
0
1
1
0
0
0
0
0
0
0
0
0
Note 4
Note 4
1
zeros
zeros
zeros
Note 6
42—43
44—47
48-4B
4C
50
51
52
16
32
32
32
8
8
06h (Hot Plug)
00h (Last item)
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Note 5
Note 5
Read Only
Read Only
Read/Write
Read Only
Read/Write
Read Only
1
0
0
0
0
0
0
0
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