參數(shù)資料
型號(hào)： OR3TP12-6PS240
英文描述： Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R
中文描述： 用戶可編程ASIC的特殊功能
文件頁數(shù)： 62/128頁
文件大小： 2450K
代理商： OR3TP12-6PS240
ORCAOR3TP12 FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
62
L Lucent Technologies Inc.
PCI Bus Core Target Controller Detailed Description
(continued)
The write data phase will follow, by deassertion of
taenn
, and assertion of Target write data enable (
twdataenn
).
twdataenn
can only be asserted while
tw_emptyn
is deasserted, indicating that write data is available in the write
data FIFOs. While
twdataenn
is asserted, the FPGA application will receive Target write data on bus
datatofpga
(with
fifo_sel
= 1), and write byte enables on
datatofpgax
. The FPGA application is informed that the last compo-
nent of the data phase is being presented when
twlastcycn
is asserted. Since this is a burst access (
datatofp-
gax[1]
= 1 during command/address phase), the
twlastcycn
is deasserted for the entire data phase expect the
last data of the write data phase. After receiving
twlastcycn
at the end of the data phase,
twdataenn
must be
deasserted by the FPGA application. See Write Data Transfer section for notes regarding data alignment on bursts.
For quad-port mode (Figure 22), the address and write data is transferred on the bus
twdata
in 16-bit segments. If
necessary, the address will be split into two 16-bit components with the LSB being transferred first. A burst opera-
tion and dual-address indication accompanies the address on
twdata[17]
and
twdata[16]
respectively. Assuming
the BAR size is greater than 16 bits, the address phase will require two clock cycles, and
twlastcycn
will be
asserted on the final or MSB component of the address. The data phase will also require two clock cycles to trans-
fer every 32-bit write data word across the 16-bit bus.
twlastcycn
will be deasserted for all 16-bit components of
the write data phase, except for the final 16-bit component where it is asserted. See Write Data Transfer section for
notes regarding write data alignment.
5-7374(F)
Figure 20. Target Memory Write Burst (PCI Bus, 32-Bit)
T0
T1
T2
T3
T4
T5
T6
T7
T8
ADDRESS
D0
D1
D2
D3
MEM WR
BE0
BE1
BE2
BE3
clk
framen
ad
c_ben
irdyn
devseln
trdyn
stopn
相關(guān)PDF資料
PDF描述
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