參數(shù)資料
型號： OR3TP12-6BA352I
英文描述： Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE
中文描述： 用戶可編程ASIC的特殊功能
文件頁數(shù)： 55/128頁
文件大?。?/td> 2450K
代理商： OR3TP12-6BA352I
Lucent Technologies Inc.
Lucent Technologies Inc.
55
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Target Controller Detailed Description
(continued)
For a write burst transaction to an odd address (
ad2
= 1), the first write data word transferred to the FPGA applica-
tion will have all its byte enables deasserted and can be discarded. For Target read transactions to an odd address
(
ad2
= 1), the first read data word provided by the FPGA application is discarded by the Target FIFO interface.
For single transaction (burst indication bit deasserted) on 32-bit PCI bus (
pci_64bit
= 0), the Target FIFO interface
handles all data alignment. The received address is valid as transferred, with the data phase aligning to this
address. No extra data is transferred or discarded.
Table 19. Target State Counter (TStateCntr) Values and the Corresponding Bus Data
TStateCntr[3:0]
Dual-Port Mode (32-bit Ports)
Quad-Port Mode (16-bit Ports)
Data on Bus
datatofpga
Adrs[31:0]
Adrs[63:32]
—
—
Data[31:0]
Data[63:32]
—
—
—
—
—
—
—
—
—
—
Data on Bus
datafmfpga
Data[31:0]
Data[63:32]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Data on Bus
twdata
Adrs[15:0]
Adrs[31:16]
Adrs[47:32]
Adrs[63:48]
Data[15:0]
Data[31:16]
Data[47:32]
Data[63:48]
—
—
—
—
—
—
—
—
Data on Bus
trdata
Data[15:0]
Data[31:16]
Data[47:32]
Data[63:48]
—
—
—
—
—
—
—
—
—
—
—
—
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
相關PDF資料
PDF描述
OR3TP12-6PS240 Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R
OR3TP12-6PS240I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R
OR3TP12 Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
OR62 OR62 is a 6-input OR gate with 2x drive strength
OR73 7-input OR gate with 3x drive strength.
相關代理商/技術參數(shù)
參數(shù)描述
OR3TP126BAN256-DB 制造商:Lattice Semiconductor Corporation 功能描述:
OR3TP12-6PS240 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP12-6PS240I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP127BA256-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3TP127BA352-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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