參數(shù)資料
型號： OR3TP12-6BA352I
英文描述： Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE
中文描述： 用戶可編程ASIC的特殊功能
文件頁數(shù)： 28/128頁
文件大?。?/td> 2450K
代理商： OR3TP12-6BA352I
ORCAOR3TP12 FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
28
L Lucent Technologies Inc.
Symbol
I/O
Description
Clock
Domain
Miscellaneous Signals
(continued)
cfgshiftenn
pci_cfg_stat
O
I
PCI Error Status Control
cfgshiftenn
is an active-low signal that MUXes the output of the PCI device
status register (PCI Specification 2.1: Section 6.2.3) onto signal
pci_cfg_stat
:
cfgshiftenn
= 1:
pci_cfg_stat
outputs the wired-OR of all status bits
below, after being masked by options in the FPSC
configuration manager.
cfgshiftenn
= 0:
pci_cfg_stat
outputs each status bit below, shifted
one at a time on successive
pciclk
rising edges.
The shift register is reset when
cfgshiftenn
= 1.
Device Status Register bits:
Detected Parity Error, Signaled System Error,
Received Master Abort, Received Target Abort,
Signaled Target Abort, Master Data Parity Error.
PCI 64-Bit Bus Indication.
This active-high signal indicates that the embed-
ded core detected that it is configured as a 64-bit agent on the PCI bus. This
is the result of detecting PCI signal
req64n
as active-low on the rising edge
of PCI signal
rstn
. Note that this does not imply that any particular transac-
tion is 64-bit, since each transaction is individually negotiated using PCI sig-
nals
req64n
and
ack64n
. When asserted, all data transfers across the
Master and Target FIFO interface will imply 64-bit data phases.
FIFO Select.
A MUX control signal that is valid in the dual-port mode to
select either Master read data (
fifo_sel
= 0) or Target address/write data
(
fifo_sel
= 1) on the
datatofpga
and
datatofpgax
bus. For quad-port mode,
this signal can be tied to high.
pciclk
pci_64bit
I
—
fifo_sel
O
—
PCI Bus Core Detailed Description
(continued)
Table 6. Embedded Core/FPGA Interface Signals
(continued)
* The source of the clock (
fclk1
or
fclk2
) for the FIFO interface (Master or Target) is selected in the FPSC configuration manager.
相關(guān)PDF資料
PDF描述
OR3TP12-6PS240 Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R
OR3TP12-6PS240I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R
OR3TP12 Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
OR62 OR62 is a 6-input OR gate with 2x drive strength
OR73 7-input OR gate with 3x drive strength.
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OR3TP126BAN256-DB 制造商:Lattice Semiconductor Corporation 功能描述:
OR3TP12-6PS240 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP12-6PS240I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP127BA256-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3TP127BA352-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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