參數(shù)資料
型號(hào)： OR3TP12-6BA352I
英文描述： Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE
中文描述： 用戶(hù)可編程ASIC的特殊功能
文件頁(yè)數(shù)： 35/128頁(yè)
文件大?。?/td> 2450K
代理商： OR3TP12-6BA352I
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Lucent Technologies Inc.
Lucent Technologies Inc.
35
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Master Controller Detailed Description
(continued)
Table 10. Bit Definitions for Master Command/Address Phase
* Refer to PCI Specification 2.3 Section 3.1.
Master Write Operation
Command/Address Setup
In order to initiate a PCI Master write operation, the FPGA application must supply the Master command and PCI
start address in the specific order prescribed in Table 13 and Table 14, for quad- and dual-port mode respectively.
This data is transferred via bus
mwdata
(quad-port mode) or
datafmfpga
(
x
) (dual-port mode) and will be accepted
by the Master FIFO interface when
ma_fulln
is inactive and
m_ready
is active. The Master command word and
address must be accompanied by assertion of the enable
maenn
, with the command/address phase ending with
the assertion of
mwlastcycn
. The bit definitions of the Master command word is shown in Table 10. For Master
writes, the same burst length bit must be equal to zero.
All burst transactions or 64-bit agents (
pci_64bit
= 1) must start transactions on a 64-bit address boundary, which
requires address bit
ad2
= 0 for the PCI start address. If the write transaction needs to start on a odd 32-bit
address boundary (
ad2
= 1), the FPGA must send a padding data word to properly fill/align the Master write data
FIFO at the beginning of the data phase. This padding data word will be the first write data word transferred from
the FPGA application, and will have all of its byte enables deasserted. When the Master starts the PCI transaction
on a 32-bit bus, this padding data word will be dropped by the Master, with the resulting transaction starting on the
odd address (
ad2
= 1).
For single 32-bit transaction on 32-bit buses (
pci_64bit
= 0), the Master FIFO interface will perform the proper data
alignment. The FPGA application will transfer the PCI starting address, even or odd, during the command/address
phase and the valid 32-bit data word during the data phase.
Bits
Name
Description
Quad-Port
Dual-Port
Master Command Word (FPGA
→
PCI Core)
17
SPL
Master Read: Same Previous Burst
Length Indication (quad-port only)
Master Write: Must Be Zero
Dual-Address Indication
Not Used
Holding Register Selector:
0 = Select HR0
1 = Select HR1
Master Read: Byte Enables
Master Write: Not Used
PCI Command Code*
mwdata[17]
datafmfpgax[3]
16
DA
—
HR
mwdata[16]
mwdata[15:13]
mwdata[12]
datafmfpgax[2]
datafmfpga[31:29]
datafmfpga[28]
15:13
12
11:4
MRDBEN
mwdata[11:4]
datafmfpga[27:20]
3:0
Cmd
mwdata[3:0]
datafmfpga[19:16]
Master Read Burst Length Word (FPGA
→
PCI Core)
17:16
BL
Burst Length of 64-bit Words
15:0
BL
Burst Length of 64-bit Words
Master Address Word (FPGA
→
PCI Core)
17:16
—
Not Used
15:0
Adrs
Address
mwdata[17:16]
mwdata[15:0]
datafmfpgax[1:0]
datafmfpga[15:0]
mwdata[17:16]
mwdata[15:0]
datafmfpgax[1:0]
datafmfpga[31:0]
相關(guān)PDF資料
PDF描述
OR3TP12-6PS240 Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R
OR3TP12-6PS240I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R
OR3TP12 Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
OR62 OR62 is a 6-input OR gate with 2x drive strength
OR73 7-input OR gate with 3x drive strength.
相關(guān)代理商/技術(shù)參數(shù)
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OR3TP126BAN256-DB 制造商:Lattice Semiconductor Corporation 功能描述:
OR3TP12-6PS240 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:User Programmable Special Function ASIC
OR3TP12-6PS240I 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:User Programmable Special Function ASIC
OR3TP127BA256-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3TP127BA352-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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