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| 型號(hào)： | OR3TP12-6BA352I |
| 英文描述： | Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE |
| 中文描述： | 用戶(hù)可編程ASIC的特殊功能 |
| 文件頁(yè)數(shù)： | 4/128頁(yè) |
| 文件大?。?/td> | 2450K |
| 代理商： | OR3TP12-6BA352I |
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Tables
Page
Tables
Page
ORCAOR3TP12 FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
4
Lucent Technologies Inc.
List of Tables
Table 1. PCI Local Bus Data Rates ...........................1
Table 2. ORCAPCI FPSC Solutions—
Available FPGA Resources..................................1
Table 3. PCI Bus Command Descriptions ...............13
Table 4. Timing Budgets..........................................17
Table 5. PCI Bus Pin Descriptions...........................18
Table 6. Embedded Core/FPGA
Interface Signals ................................................21
Table 7. OR3TP12 FPGA/PCI Core
Interface Signal Locations..................................29
Table 8. PCI Bus Core Options Settable
via FPGA Configuration RAM Bits ....................31
Table 9. Index to State Sequence Tables.................33
Table 10. Bit Definitions for Master
Command/Address Phase.................................35
Table 11. Holding Registers,
Examples of Typical Operation...........................36
Table 12. Master State Counter (MStateCntr)
Values and the Corresponding Bus Data...........36
Table 13. Dual-Port Master Writes...........................43
Table 14. Quad-Port Master Writes .........................43
Table 15. Dual-Port Master Read,
Specified Burst Length.......................................51
Table 16. Quad-Port Master Read,
Duplicate Burst Length.......................................52
Table 17. Quad-Port Master Read,
Specified Burst Length.......................................52
Table 18. Bit Destinations for Target
Command/Address Phase.................................54
Table 19. Target State Counter (TStateCntr)
Values and the Corresponding Bus Data...........55
Table 20. Dual-Port Target Write..............................64
Table 21. Quad-Port Target Write ............................65
Table 22. Dual-Port Target Read .............................79
Table 23. Quad-Port Target Read............................79
Table 24. Configuration Space Layout.....................82
Table 25. Configuration Space Assignment.............83
Table 26. Configuration Frame
Format and Contents .........................................89
Table 27. Configuration Frame Size.........................90
Table 28. Configuration Modes................................90
Table 29. Absolute Maximum Ratings .....................91
Table 30. Recommend Operating Conditions..........91
Table 31. Electrical Characteristics..........................92
Table 32. Derating for Commercial Devices
(I/O Supply V
DD
) ................................................93
Table 33. OR3TP12 PCI and FPGA Interface
Clock Operation Frequencies.............................95
Table 34. OR3TP12 FPGA to PCI, and PCI to
FPGA, Combinatorial Path Delays.....................95
Table 35. OR3TP12 FPGA Side Interface
Combinatorial Path Delay Signals......................96
Table 36. OR3TP12 Interbuf Delays ........................96
Table 37. OR3TP12 FPGA Side Interface Clock to
Output Delays, pciclk Synchronous Signals.......97
Table 38. OR3TP12 FPGA Side Interface Clock to
Output Delays, fclk Synchronous Signals ..........97
Table 39. OR3TP12 FPGA Side Interface Input
Setup Delays, pciclk Synchronous Signals........98
Table 40. OR3TP12 FPGA Side Interface Input
Setup Delays, fclk Synchronous Signals............98
Table 41. FPGA Common-Function
Pin Descriptions...............................................102
Table 42. OR3TP12 240-Pin SQFP2 Pinout..........105
Table 43. OR3TP12 256-Pin PBGA Pinout............109
Table 44. OR3TP12 352-Pin PBGA Pinout............113
Table 45. ORCA OR3TP12 Plastic Package
Thermal Guidelines..........................................120
Table 46. ORCA OR3TP12 Package Parasitics.....121
Table 47. Voltage Options......................................126
Table 48. Temperature Options..............................126
Table 49. Package Options....................................126
Table 50. ORCA Series 3+ Package Matrix...........126
Table 51. Embedded Core Type.............................126
Table 52. FPSC Base Array...................................126
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR3TP12-6PS240 | Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R |
| OR3TP12-6PS240I | Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R |
| OR3TP12 | Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface |
| OR62 | OR62 is a 6-input OR gate with 2x drive strength |
| OR73 | 7-input OR gate with 3x drive strength. |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3TP126BAN256-DB | 制造商:Lattice Semiconductor Corporation 功能描述: |
| OR3TP12-6PS240 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:User Programmable Special Function ASIC |
| OR3TP12-6PS240I | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:User Programmable Special Function ASIC |
| OR3TP127BA256-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3TP127BA352-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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