參數(shù)資料
型號： OR3TP12-6BA256I
英文描述： Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, TUBE
中文描述： 用戶可編程ASIC的特殊功能
文件頁數(shù)： 77/128頁
文件大?。?/td> 2450K
代理商： OR3TP12-6BA256I
Lucent Technologies Inc.
Lucent Technologies Inc.
77
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Target Controller Detailed Description
(continued)
5-7365(F)
Figure 32. Target Read Burst (FIFO Interface, Quad-Port)
Target Read Memory Burst, Nondelayed Transaction
Figure 33 shows the timing on the PCI bus interface, for a Target memory burst read of four 32-bit words handled
as a nondelayed transaction (
deltrn
= 1,
trburstpendn
= 0). The operation starts and waits on the PCI bus while
the FPGA application is notified via the Target FIFO Interface. This is similar to that of an delayed Target burst read
(Figure 30), except the Target accepts the transaction without issuing an immediate retry, but inserts wait-states
(up to 16 or 32) until data is in placed in the Target read FIFO. If the FPGA application cannot provide data within
the initial latency time, the Target issues a retry.
Target Read Burst FIFO Interface
The timing on the FPGA interface (Figure 31 for dual-port) shows the first indication to the FPGA application that a
new operation has begun by the assertion of Target request (
treqn
). The FPGA application begins the command/
address phase by asserting Target address enable (
taenn
) and accepting the command from the
tcmd
bus and
address from bus
datatofpga[0]
(with
fifo_sel
= 1). A burst operation and dual-address indication accompanies
the address on
datatofpgax[1]
and
datatofpgax[0]
respectively. The FPGA application continues to receives
address data until
twlastcycn
is asserted indicating the end of the command/address phase. See Command/
Address Setup section (see page 54) for notes on address transfer and alignment.
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
0
1
0
1
2
3
0
1
2
3
0
CMD
ADRS0
ADRS1
D0
D1
D2
D3
D4
D5
D6
D7
fclk
t_ready
tstatecntr
treqn
tcmd
twdata
taenn
twlastcycn
trdata
tr_fulln
trdataenn
trlastcycn
相關PDF資料
PDF描述
OR3TP12-6BA352 Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-PDIP, TUBE
OR3TP12-6BA352I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE
OR3TP12-6PS240 Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R
OR3TP12-6PS240I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R
OR3TP12 Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
相關代理商/技術參數(shù)
參數(shù)描述
OR3TP126BA256I-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3TP12-6BA352 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP126BA352-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3TP12-6BA352I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP126BAN256-DB 制造商:Lattice Semiconductor Corporation 功能描述:
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