參數(shù)資料
型號： OR3TP12-6BA256I
英文描述： Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, TUBE
中文描述： 用戶可編程ASIC的特殊功能
文件頁數(shù)： 19/128頁
文件大?。?/td> 2450K
代理商： OR3TP12-6BA256I
Lucent Technologies Inc.
Lucent Technologies Inc.
19
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Detailed Description
(continued)
Table 5. PCI Bus Pin Descriptions
(continued)
Symbol
I/O
Description
Interface Control Pins
(continued)
irdyn
I/O
Initiator Ready.
An active-low signal indicating the bus Master’s ability to complete
the current data phase of the transaction.
irdyn
is used in conjunction with
trdyn
. A
data phase is completed on any clock cycle during which both
irdyn
and
trdyn
are
asserted. During a write,
irdyn
indicates that valid data from the Master is present
on the
ad
bus. During a read, it indicates that the Master is prepared to accept data.
Wait cycles are inserted until both
irdyn
and
trdyn
are asserted together.
Target Ready.
An active-low signal asserted to indicate the readiness of the Tar-
get’s agent to complete the current data phase of the transaction.
trdyn
is used in
conjunction with
irdyn
. A data phase is completed on any clock where both
trdyn
and
irdyn
are sampled active. During reads,
trdyn
indicates that valid data from the
Target is present on the
ad
bus. During write cycles,
trdyn
indicates that the Target
is prepared to accept data.
Stop.
Indicates that the current Target is requesting the Master to stop the current
transaction.
Initialization Device Select.
Used as a chip select during PCI configuration read
and write transactions. Generally, the user ties
idsel
to one of the upper 24 address
lines,
ad[31:8]
.
Device Select.
An active-low signal indicating that a Target device on the bus has
been selected. As an output, it indicates that the driving device has decoded its
address as the Target of the current access.
Arbitration Pins (for Bus Master Only)
reqn
O
Request.
An active-low signal that indicates to the arbiter that the asserting agent
desires use of the bus. In the OR3TP12, this signal is asserted when the OR3TP12
Master controller needs access to the PCI bus.
gntn
I
Grant.
An active-low signal that indicates to the OR3TP12 Master that access to
the PCI bus has been granted.
Error Reporting Pins
perrn
I/O
Parity Error.
An active-low signal for the reporting of data parity errors during all
PCI transactions except a special cycle. The
perrn
pin is a sustained 3-state signal
and must be driven active by the agent receiving data two clocks following the data
when a data parity error is detected. The minimum duration of
perrn
is one clock for
each data phase that a data parity error is detected. If sequential data phases each
have a data parity error, the
perrn
signal will be asserted for more than a single
clock.
perrn
is driven high for one clock before being 3-stated.
perrn
is not
asserted until it has claimed the access by asserting
devseln
and completed a
data phase.
serrn
O
System Error.
An active-low signal pulsed by agents to report errors other than
data parity.
serrn
is sampled every
clk
edge, so any agent asserting
serrn
must
ensure it is valid for at least one clock period. For example,
serrn
can be asserted if
an abort sequence is detected by the Master, or an address parity error is detected
by the Target.
trdyn
I/O
stopn
I/O
idsel
I
devseln
I/O
相關(guān)PDF資料
PDF描述
OR3TP12-6BA352 Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-PDIP, TUBE
OR3TP12-6BA352I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE
OR3TP12-6PS240 Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R
OR3TP12-6PS240I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R
OR3TP12 Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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OR3TP126BAN256-DB 制造商:Lattice Semiconductor Corporation 功能描述:
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