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| 型號： | OR3T556PS240-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 324 CLBS, 80000 GATES, PQFP240 |
| 封裝： | PLASTIC, SQFP2-240 |
| 文件頁數(shù)： | 55/203頁 |
| 文件大?。?/td> | 1368K |
| 代理商： | OR3T556PS240-DB |
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148
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Pin Information (continued)
Table 67. Pin Descriptions (continued)
Symbol
I/O
Description
Special-Purpose Pins
(continued)
M3
I
I/O
During powerup and initialization, M3 is used to select the speed of the internal oscillator dur-
ing conguration with their values latched on the rising edge of INIT. When M3 is low, the oscil-
lator frequency is 10 MHz. When M3 is high, the oscillator is 1.25 MHz. During conguration,
a pull-up is enabled.
After conguration, this pin is a user-programmable I/O pin (see Note).
TDI, TCK,
TMS
I
I/O
If boundary scan is used, these pins are test data in, test clock, and test mode select inputs. If
boundary scan is not selected, all boundary-scan functions are inhibited once conguration is
complete. Even if boundary scan is not used, either TCK or TMS must be held at logic 1 dur-
ing conguration. Each pin has a pull-up enabled during conguration.
After conguration, these pins are user-programmable I/O (see Note).
RDY/RCLK/
MPI_ALE
O
I
I/O
During conguration in peripheral mode, RDY/RCLK indicates another byte can be written to
the FPGA. If a read operation is done when the device is selected, the same status is also
available on D7 in asynchronous peripheral mode.
During the master parallel conguration mode, RCLK is a read output signal to an external
memory. This output is not normally used.
In
i960 microprocessor mode, this pin acts as the address latch enable (ALE) input.
After conguration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note).
HDC
O
I/O
High During Conguration is output high until conguration is complete. It is used as a control
output, indicating that conguration is not complete.
After conguration, this pin is a user-programmable I/O pin (see Note).
LDC
O
I/O
Low During Conguration
is output low until conguration is complete. It is used as a control out-
put, indicating that conguration is not complete.
After conguration, this pin is a user-programmable I/O pin (see Note).
INIT
I/O
INIT
is a bidirectional signal before and during conguration. During conguration, a pull-up is
enabled, but an external pull-up resistor is recommended. As an active-low open-drain out-
put, INIT is held low during power stabilization and internal clearing of memory. As an active-
low input, INIT holds the FPGA in the wait-state before the start of conguration.
After conguration, this pin is a user-programmable I/O pin (see Note).
Note: The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE
release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other conguration pins (and the
activation of all user I/Os) is controlled by a second set of options.
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| OR3T55-6PS240I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T556PS240I-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 2592 LUT 288 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3T556S208-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 Use LatticeEC RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3T556S208I-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 Use LatticeEC RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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