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參數(shù)資料
| 型號(hào)： | OR3T556PS240-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 324 CLBS, 80000 GATES, PQFP240 |
| 封裝： | PLASTIC, SQFP2-240 |
| 文件頁數(shù)： | 179/203頁 |
| 文件大?。?/td> | 1368K |
| 代理商： | OR3T556PS240-DB |
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Lattice Semiconductor
77
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Clock Manager (PCM)
(continued)
PCM/FPGA Internal Interface
Writing and reading the PCM registers is done through
a simple asynchronous interface that connects with the
FPGA routing resources. Reads from the PCM by the
FPGA logic are accomplished by setting up the 3-bit
address, A[2:0], and then applying an active-high read
enable (RE) pulse. The read data will be available as
long as RE is held high. The address may be changed
while RE is high, to read other addresses. When RE
goes low, the data output bus is 3-stated.
Writes to the PCM by the FPGA logic are performed by
applying the write data to the data input bus of the
PCM
, applying the 3-bit address to write to, and assert-
ing the write enable (WE) signal high. Data will be writ-
ten by the high-going transition of the WE pulse.
The read enable (RE) and write enable (WE) signals
may not be active at the same time. For detailed timing
information and specications, see the Timing Charac-
teristics section of this data sheet.
The LOCK signal output from the PCM to the FPGA
routing indicates a stable output clock signal from the
PCM
. The LOCK signal is high when the PCM output
clock parameters fall within the programmed values
and the PCM specications for jitter. Due to phase cor-
rections that occur internal to the PCM, the LOCK sig-
nal might occasionally pulse low when the output clock
is out of specication for only one or two clock cycles
(high jitter due to temperature, voltage uctuation, etc.)
To accommodate these pulses, it is suggested that the
user integrate the LOCK signal over a period suitable
to their application to achieve the desired usage of the
LOCK signal.
The LOCK signal will also pulse high and low during
the acquisition time as the output clock stabilizes. True
LOCK is only achieved when the LOCK signal is a solid
high. Again, it is suggested that the user integrate the
LOCK signal over a time period suitable to the subject
application.
PCM Operation
Several features are available for the control of the
PCM
’s overall operation. The PCM may be programma-
bly enabled/disabled via bit 0 of register 7. When dis-
abled, the analog power supply of the PCM is turned
off, conserving power and eliminating the possibility of
inducing noise into the system power buses. Individual
bits (register 7, bits [2:1]) are provided to reset the DLL
and PLL functions of the PCM. These resets affect only
the logic generating the DLL or PLL function; they do
not reset the divider values (DIV0, DIV1, DIV2) or reg-
isters [7:0]. The global set/reset (GSRN) is also pro-
grammably controlled via register 7, bit 7. If register 7,
bit 7 is set to 1, GSRN will have no effect on the PCM
logic, allowing the clock to operate during a global
set/reset. This function allows the FPGA to be reset
without affecting a clock that is sent off-chip and used
elsewhere in the system. Bit 6 of register 7 affects the
functionality of the PCM during conguration. If set to 1,
this bit enables the PCM to operate during congura-
tion, after the PCM has been congured. The PCM
functionality is programmed via the bit stream. If regis-
ter 7, bit 6 is 0, the PCM cannot function and its power
supply is disabled until after the conguration DONE
signal goes high.
When the PCM is powered up via register 7, bit 0, there
is a wake-up time associated with its operation. Follow-
ing the wake-up time, the PCM will begin to fully func-
tion, and, following an acquisition time during which the
output clock may be unstable, the PCM will be in
steady-state operation. There is also a shutdown time
associated with powering off the PCM. The output clock
will be unstable during this period. Waveforms and tim-
ing parameters can be found in the Timing Characteris-
tics section of this data sheet.
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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| OR3T55-6PS240I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
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