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| 型號(hào)： | OR3T307S240-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 196 CLBS, 48000 GATES, PQFP240 |
| 封裝： | PLASTIC, SQFP-240 |
| 文件頁(yè)數(shù)： | 17/203頁(yè) |
| 文件大小： | 1368K |
| 代理商： | OR3T307S240-DB |
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Lattice Semiconductor
113
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Special Function Blocks Timing
Table 49. Microprocessor Interface (MP I)Timing Characteristics
OR3Cxx Commercial: VDD = 5.0 V ± 5%, 0 °C
< TA < 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C < TA < +85 °C.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C
< TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.
1. For user system exibility, CS0 and CS1 may be set up to any one of the three rising clock edges, beginning with the rising clock edge when
MPI_STRB
is low. If both chip selects are valid and the setup time is met, the MPI will latch the chip select state, and CS0 and CS1 may go
inactive before the end of the read/write cycle.
2. 0.5 MPI_CLK.
3. Write data and W/R have to be valid starting from the clock cycle after both ADS and CS0 and CS1 are recognized.
4. Write data and W/R have to be held until the microprocessor receives a valid RDYRCV.
Notes:
Read and write descriptions are referenced to the host microprocessor; e.g., a read is a read by the host (
PowerPC, i960) from the FPGA.
PowerPC and i960 timings to/from the clock are relative to the clock at the FPGA microprocessor interface clock pin (MPI_CLK).
Parameter
Symbol
Speed
Unit
–4
–5
–6
–7
Min Max Min Max Min Max Min Max
PowerPC Interface Timing
(TJ = 85 °C, VDD = min)
Transfer Acknowledge Delay (CLK to TA)
Burst Inhibit Delay (CLK to BIN)
Transfer Acknowledge Delay to High Impedance
Burst Inhibit Delay to High Impedance
Write Data Setup Time (data to TS)
Write Data Hold Time (data from CLK while MPI_ACK low)
Address Setup Time (addr to TS)
Address Hold Time (addr from CLK while MPI_ACK low)
Read/Write Setup Time (R/W to TS)
Read/Write Hold Time (R/W from CLK while MPI_ACK low)
Chip Select Setup Time (CS0, CS1 to TS)
Chip Select Hold Time (CS0, CS1 from CLK)
User Address Delay (pad to UA[3:0])
User Read/Write Delay (pad to URDWR_DEL)
TA_DEL
BI_DEL
TA_DELZ
BI_DELZ
WD_SET
WD_HLD
A_SET
A_HLD
RW_SET
RW_HLD
CS_SET
CS_HLD
UA_DEL
URDWR_DEL
—
0.0
0.3
0.0
—
11.6
(2)
—
3.3
7.0
—
0.0
.25
0.0
—
9.3
(2)
—
2.6
5.4
—
0.0
.14
0.0
—
8.0
(2)
—
2.3
4.2
—
0.0
.12
0.0
—
6.8
(2)
—
1.9
3.6
ns
i960 Interface Timing
(TJ = 85 °C, VDD = min)
Addr/Data Select to ALE (ADS, to ALE low)
Addr/Data Select to ALE (ADS, from ALE low)
Ready/Receive Delay (CLK to RDYRCV)
Ready/Receive Delay to High Impedance
Write Data Setup Time
Write Data Hold Time
Address Setup Time (addr to ALE low)
Address Hold Time (addr from ALE low)
Byte Enable Setup Time (BE0, BE1 to ALE low)
Byte Enable Hold Time (BE0, BE1 from ALE low)
Read/Write Setup Time
Read/Write Hold Time
Chip Select Setup Time (CS0, CS1 to CLK)(1)
Chip Select Hold Time (CS0, CS1 from CLK)(1)
User Address Delay (CLK low to UA[3:0])
User Read/Write Delay (pad to URDWR_DEL)
ADSN_SET
ADSN_HLD
RDYRCV_DEL
RDYRCV_DELZ
WD_SET
WD_HLD
A_SET
A_HLD
BE_SET
BE_HLD
RW_SET
RW_HLD
CS_SET
CS_HLD
UA_DEL
URDWR_DEL
2.0
0.0
—
(3)
(4)
2.0
(3)
(4)
2.0
0.0
—
11.6
(2)
—
6.6
7.0
1.8
0.0
—
(3)
(4)
1.8
(3)
(4)
1.8
0.0
—
9.3
(2)
—
4.3
5.4
1.6
0.0
—
(3)
(4)
0.50
0.51
0.50
0.51
(3)
(4)
0.45
0.0
—
8.0
(2)
—
4.1
4.2
1.4
0.0
—
(3)
(4)
—
(3)
(4)
—
0.0
—
6.8
(2)
—
0.42
0.44
0.42
0.44
—
0.38
—
3.5
3.6
ns
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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| OR3T556PS240-DB | FPGA, 324 CLBS, 80000 GATES, PQFP240 |
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相關(guān)代理商/技術(shù)參數(shù) |
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| OR3T30-7S240I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T55 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
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| OR3T55-4PS240I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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