參數(shù)資料
型號(hào)： OR3T1257PS208-DB
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 784 CLBS, 186000 GATES, PQFP208
封裝： PLASTIC, SQFP2-208
文件頁(yè)數(shù)： 199/203頁(yè)
文件大?。?/td> 1368K
代理商： OR3T1257PS208-DB
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Lattice Semiconductor
95
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
FPGA Conguration Modes (continued)
Slave Serial Mode
The slave serial mode is primarily used when multiple
FPGAs are congured in a daisy-chain (see the Daisy-
Chaining section). It is also used on the FPGA evalua-
tion board that interfaces to the download cable. A
device in the slave serial mode can be used as the lead
device in a daisy-chain. Figure 61 shows the connec-
tions for the slave serial conguration mode.
The conguration data is provided into the FPGA’s DIN
input synchronous with the conguration clock CCLK
input. After the FPGA has loaded its conguration data,
it retransmits the incoming conguration data on
DOUT. CCLK is routed into all slave serial mode
devices in parallel.
Multiple slave FPGAs can be loaded with identical con-
gurations simultaneously. This is done by loading the
conguration data into the DIN inputs in parallel.
5-4485(F)
Figure 61. Slave Serial Conguration Schematic
Slave Parallel Mode
The slave parallel mode is essentially the same as the
slave serial mode except that 8 bits of data are input on
pins D[7:0] for each CCLK cycle. Due to 8 bits of data
being input per CCLK cycle, the DOUT pin does not
contain a valid bit stream for slave parallel mode. As a
result, the lead device cannot be used in the slave
parallel mode in a daisy-chain conguration.
Figure 62 is a schematic of the connections for the
slave parallel conguration mode. WR and CS0 are
active-low chip select signals, and CS1 is an active-
high chip select signal. These chip selects allow the
user to congure multiple FPGAs in slave parallel
mode using an 8-bit data bus common to all of the
FPGAs. These chip selects can then be used to select
the FPGA(s) to be congured with a given bit stream.
The chip selects must be active for each valid CCLK
cycle until the device has been completely pro-
grammed. They can be inactive between cycles but
must meet the setup and hold times for each valid pos-
itive CCLK. D[7:0] of the FPGA can be connected to
D[7:0] of the microprocessor only if a standard prom
le format is used. If a .bit or .rbt le is used from
ispLEVER, then the user must mirror the bytes in the
.bit or .rbt le OR leave the .bit or .rbt le unchanged
and connect D[7:0] of the FPGA to D[0:7] of the micro-
processor.
5-4487(F)
Figure 62. Slave Parallel Conguration Schematic
MICRO-
PROCESSOR
OR
DOWNLOAD
CABLE
M2
M1
M0
HDC
SERIES
FPGA
LDC
VDD
CCLK
PRGM
DOUT
TO DAISY-
CHAINED
DEVICES
DONE
DIN
INIT
ORCA
MICRO-
PROCESSOR
OR
SYSTEM
D[7:0]
DONE
CCLK
CS1
M2
M1
M0
HDC
LDC
8
VDD
INIT
PRGM
CS0
WR
SERIES
FPGA
ORCA
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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