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參數(shù)資料
| 型號(hào)： | OR3T1257PS208-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 784 CLBS, 186000 GATES, PQFP208 |
| 封裝： | PLASTIC, SQFP2-208 |
| 文件頁(yè)數(shù)： | 148/203頁(yè) |
| 文件大?。?/td> | 1368K |
| 代理商： | OR3T1257PS208-DB |
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Lattice Semiconductor
49
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Clock Distribution Network (continued)
Clock Distribution in the PLC Array
System Clock (SCLK)
The clock distribution network, or clock spine network,
within the PLC array is designed to minimize clock
skew while maximizing clock exibility. Clock exibility is
expressed in two ways: the ease with which a single
clock is routed to the entire array, and the capability to
provide multiple clocks to the PLC array.
There is one horizontal and one vertical clock spine
passing through each PLC. The horizontal clock spine
is sourced from the PIC in the same row on either the
left- or right-hand side of the array, with the source side
(left or right) alternating for each row. The vertical clock
spines are similarly sourced from the PICs alternating
from the top or bottom of a column. Each clock spine is
capable of driving one of the ten xL routing segments
that run orthogonal to it within each PLC. Full connec-
tivity to all PFUs is maintained due to the connectivity
from the xL lines to the PFU clock signals described in
the previous section; however, only an xL line in every
other row (column) needs to be driven to allow the
given clock signal to be distributed to every PFU.
Figure 32 is a high-level diagram of the Series 3 system
clock spine network with sample xL line
connections for a 4 x 4 array of PLCs.
The clock spine structure previously described pro-
vides for complete distribution of a clock from any I/O
pin to the entire PLC array by means of a single clock
spine and long lines (xL). This distribution system also
provides a means to have many different clocks routed
to many different and dispersed locations in the PLC
array. Each spine can carry a different clock signal, so
for the OR3T55 (which has an 18 x 18 array of PLCs,
implying nine clock spines per side), 36 input clock sig-
nals can be supported using the system clock network.
Fast Clock
Fast clocks are high-speed, low-skew clock spines that
originate from the CLKCNTRL special function blocks
(described later). There are four fast clock spines—one
originating on the middle of each edge of the array. The
spines run in the interquad region of the PLC array
from their source side of the device to the last row or
column on the opposite side of the device. The fast
clocks connect to two long lines, xL[8] and xL[9], that
run orthogonal to the spine direction in each PLC.
These long lines can then be connected to the PFU
clock input in the same manner as the general system
clocks, and, like the system clock connections, xL lines
are only needed in every other row (column) to distrib-
ute a clock to every PFU. The limited number of long-
line connections and the low skew of the CLKCNTRL
source combine to make the fast clocks a very robust,
low-skew clock source.
5-5801(F).a
Figure 32.
ORCA Series 3 System Clock Distribution Overview
(xL)
HORIZONTAL
(xL)
UNUSED
(xL)
UNUSED
SCLK SPINE
(xL)
UNUSED
SCLK SPINE
VERTICAL
SCLK SPINE
UNUSED
SCLK SPINE
UNUSED
SCLK SPINE
UNUSED
SCLK SPINE
UNUSED
SCLK SPINE
UNUSED
SCLK SPINE
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3T125-7PS208I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
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| OR3T1257PS240-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 6272 LUT 342 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3T125-7PS240I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T20 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
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